How many logic cells are there in one slice

XC2V3000

Step 1: go to

Step 2: type in the following three words: logic cell slice Step 3: click on the 4th result

Marc

The 4th result of google will change frequently...

I think the OP is confused by the fact the Xilinx count a slice as 2.25 LCs due to "extra features".

A hint for Xilinx marketing: They could also increase the I/O-count by 7.8% due to extra features ;-)

Seriously: I think Altera has more sophisticated counter and register-packing, so this 2.25-factor is very misleading. Things look different when we are talking about Stratix II - ALMs, where I would not really back up Altera's +25%-claim, too (at least what I see from a larger test-design, originally targeted to Cyclone).

Thomas

Thomas Entner wrote: [...]

by 7.8%

Indeed. In fact, I can't help but think it's more than just 7.8%! The mind boggles just thinking of all the ways their marketing department could find justification for saying that a 456 pin device has "effectively 2000 pins".

not

larger

Agreed. Inflating their (Xilinx or Altera) numbers by 25% implies to me that, I should find the "extra features" being used in one out of four logic cells, on average. Instead, I find that on a 20000 LUT design, 2000 MUXFx's are used. So for this design, it's really 10% - and that was coding by our ASIC guys, who tend to not pipeline as much as they could/should. On our other designs, it is noticably below 10%.

Have fun,

Marc

Hi Thomas,

The 2.5 Stratix LEs to Stratix II ALM ratio is an average over a large suite of (real) designs. That said, there *is* a spread to the LE to ALM ratio. An (artificial) design that maps perfectly into 4-LUTs will get a ~2:1 ratio. An (artificial) design comprising all random 6-LUTs will get a ~4:1 ratio. Real designs will land somewhere in between as they will use a variety of various LUT types. Also, the amount of arithmetic circuitry and # of FFs in the design can impact the packing ratio.

From an intuitive perspective, just look at the ALM and you can see that there is a lot more goo there than just what would be needed for 2 LEs. That extra circuitry isn't free -- we would not have spent that silicon area on it without getting more logic density back. Otherwise we would have just removed the circuitry and instead fit more LEs in the chip!

Regards,

Paul Leventis Altera Corp.

Depends on your exact definition of a logic cell.

If a logic cell is "one 4-LUT and one FF", then a slice (a xilinx term) contains 2 of them. The slice contains other stuff that is not part of the above definition of a logic cell, and the logic cell (LUT+FF) can do stuff beyond the minimum of what you would expect a "4-LUT + FF" can do (such as SP RAM, DP RAM, SRL16, carry).

According to

the XC2V3000 has:

28672 4-LUTS 28672 FFs (in the slices. there are 720 I/Os that also have FFs)

A slice contains the following: Slice (2 x (FF+Carry+XOR+AND+LUT4(as Logic/ROM/RAM/Shifter) )

Philip

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