help:dual-edge flip-flop possible using Verilog?

Yes, see my earlier comment about CLK_min, that meant not FREQ, but the HI and LOW minimum times that all clocks have. Such a circuit will generate needle pulse clocks, so you will need to watch the Min pulse widths.

-jg

If you really need to clock a flip-flop on both clock edges, the circuit described in the recent posting by Bob Perlman (and apparently originated by Gabor, whom I have contacted and congratulated) is really much better and cleaner than my frequency doubler. Maybe a bit more expensive, but flip-flops and XORs are cheap, and headaches are expensive. Peter Alfke, from home

If you really need to clock a flip-flop on both clock edges, the circuit described in the recent posting by Bob Perlman (and apparently originated by Gabor, whom I have contacted and congratulated) is really much better and cleaner than my frequency doubler. Maybe a bit more expensive, but flip-flops and XORs are cheap, and headaches are expensive. Peter Alfke, from home

Thanks! I use the circuit posted by Bob Perlman to construct a FSM just now and the performance of timing verification via QuartusII seems to be good. I think this may be a solution, but I whether I made the best choice to construct the module. Requirement:

*the work freq is 640Khz *the expected datarate is 640K, 320K, 160K *since this chip will be passive (without battery), power consumption is very important *when datarate is 640K, either higher freq (at the cost of higher power consumption) or det(at the cost of larger area) have to be introduced; while datarate is lower than 640K, neither is needed. Then, I have three ways to choose from: *a whole module using det-FSM advantage: only one Fsm disadvantage: extra control part, to decide whether negedge of clk is active *a module consisting of a det-FSM part and a set-FSM (single-edge-trigged FSM) part advantage: easy to realize disadvantage: two groups of state registers *a module using higher freq, esp. 1.28Mhz advantage: small area disadvantage: higher power consumption I am now making a module consisting of a det and a set FSM, but I am not sure whether I am making the best choice. Every advice would be highly appreciated. Best Regards, Yuqing Youth

What is your design actually doing? And is an FPGA actually the correct solution? When you are talking about relatively low frequencies, and very low power requirements, you might be better off using a microcontroller - depending of course on what the data is, and what you are trying to do with it.

Thanks! At the end we will implement our design to a chip by asic tech, and now we are designing and verifying via Fpga. That is why the freq and power are always on our list. Best Regards, YuQing Youth