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Re: help:dual-edge flip-flop possible using Verilog?
Thanks
I have done some work using this circuit and it seems to function well.
Since the clk is 640Khz, the requirement of clk_min should be
satisfied.
I have another two aspects:
*the width of pulses generated by this circuit, and
*the delay caused by this circuit
whether these two are safe when implementing the design by asic tech?

As a learner with little experience, every reply give me great help and
will be highly appreciated.


Re: help:dual-edge flip-flop possible using Verilog?
If you really need to clock a flip-flop on both clock edges, the
circuit described in the recent posting by Bob Perlman (and apparently
originated by Gabor, whom I have contacted and congratulated) is really
much better and cleaner than my frequency doubler. Maybe a bit more
expensive, but flip-flops and XORs are cheap, and headaches are
expensive.
Peter Alfke, from home


Re: help:dual-edge flip-flop possible using Verilog?
Thanks!
I use the circuit posted by Bob Perlman to construct a FSM just now and
the performance of timing verification via QuartusII seems to be good.
I think this may be a solution, but I whether I made the best choice to
construct the module.
Requirement:
*the work freq is 640Khz
*the expected datarate is 640K, 320K, 160K
*since this chip will be passive (without battery), power consumption
is very important
*when datarate is 640K, either higher freq (at the cost of higher power
consumption) or det(at the cost of larger area) have to be introduced;
while datarate is lower than 640K, neither is needed.
Then, I have three ways to choose from:
*a whole module using det-FSM
advantage: only one Fsm
disadvantage: extra control part, to decide whether negedge of clk is
active
*a module consisting of a det-FSM part and a set-FSM
(single-edge-trigged FSM) part
advantage: easy to realize
disadvantage:  two groups of state registers
*a module using higher freq, esp. 1.28Mhz
advantage: small area
disadvantage: higher power consumption
I am now making a module consisting of a det and a set FSM, but I am
not sure whether I am making the best choice.
Every advice would be highly appreciated.
Best Regards,
Yuqing Youth


Re: help:dual-edge flip-flop possible using Verilog?
Quoted text here. Click to load it

What is your design actually doing?  And is an FPGA actually the correct
solution?  When you are talking about relatively low frequencies, and
very low power requirements, you might be better off using a
microcontroller - depending of course on what the data is, and what you
are trying to do with it.

Re: help:dual-edge flip-flop possible using Verilog?
Thanks!
At the end we will implement our design to a chip by asic tech, and now
we are designing and verifying via Fpga.
That is why the freq and power are always on our list.
Best Regards,
YuQing Youth


Re: help:dual-edge flip-flop possible using Verilog?
If you really need to clock a flip-flop on both clock edges, the
circuit described in the recent posting by Bob Perlman (and apparently
originated by Gabor, whom I have contacted and congratulated) is really
much better and cleaner than my frequency doubler. Maybe a bit more
expensive, but flip-flops and XORs are cheap, and headaches are
expensive.
Peter Alfke, from home


Re: help:dual-edge flip-flop possible using Verilog?
Hi -

I kind of like a DDR FF emulation circuit that Gabor described in a
post last May; see the drawing below (please view with fixed-width
fonts).  You use two D FFs and three XORs to create the function of a
FF that clocks on both edges.  The extra gates at the inputs and
outputs mean that the setup time and CP-to-Q delays suffer somewhat,
but the Q output is glitch-free.



                       -----------------------.
                       |                      |
                       |  __                  |
                       '-\ \       .--o--.   |
                          || |------|D S Q'-o-)--.
                      .--//_/       |     | | |  |
                      |        .----|>    | | |  |
                      |        |    |  R Q| | |  |
                      |        |    '--o--' | |  |   __
           DIN  ------o        |            | |  '--\ \
                      |        |            | |      || |- Q
           CLK  ------)--------o            | |  ---//_/
                      |   __   |            | |  |
                      '--\ \  |    .--o--. | |  |
                          || |-)----|D S Q'-)-o--'
                        -//_/  |    |     | |
                       |       '---o|>    | |
                       |            |  R Q| |
                       |            '--o--' |
                       |                    |
                       '--------------------'

Me, if my circuit were operating at low speed, I'd probably just use a
2X clock.  And I agree with Symon that gating the clock line is
something you do only if you have no other choice, and then only if
you understand the implications (I'm sure Peter understands them, but
those new to design may not).

Bob Perlman
Cambrian Design Works
http://www.cambriandesign.com
and
http://www.sonic.net/~bobperl/blogger/2006/01/clock-gating-just-say-no.html

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