Hello Everyone again,
This topic is troubling me for couple of weeks now. I want to get over this as quickly as possible. I am trying to transmit data from the virtex 4 LX fpga board to the PC using ethernet PHY and i am unable to detect any data on the PC. I have written a small state machine using vhdl which actually transmits the ethernet packet( dest MAC, Source MAC, length/type, data, fcs(Crc)] . I am sure that FCS is correct as i tested my code for sample ethernet packets and i got it right.
There is a sample bit file given with the evaluation board to me for testing the ethernet PHY.So when i download this bit file and in the cmd , when i say ping fpga(mac address) and i start the ethereal capture. I am able to see the data transfer to and from between fpga and mac. But if i dont ping it and just start capturing by clicking the capture, i am not able to detect anything except the ARP which is data transferred from PCs ip address to broadcast.
In my project i dont ping in the cmd because i didnt include any ip address in my vhdl code. So basically i am not able to detect anything in the ethereal except the ARP which is being transferred from PC to broadcast. The format of the ethernet frame i am using is Destination MAC ad, Source MAC, length/type, data, FCS(CRC) and i am not using any ip address or udp header in my ethernet frame in the vhdl code.
Probably the data is getting transferred on to the PC, but not able to capture it since, i am not pinging it. So how do we see what data is coming out from the PHY.
Please advice ?
Thanks Ashwin