I'm going to talk to a potential new client about using FPGAs to accelerate part of their system.
As part of what needs done there could be a significant amount of division(s) done.
Previously I've been able to multiply by a reciprocal then scale to make division a double clock operation so this can be easily pipelined. This is only achieveable if the divisor is pre-known and the reciprocal can be pre-calculated.
With what's coming up I'm not sure that I can do this, I know that
Are there any clever techniques for streamlining divisions that make them deterministic and don't use a big wodge of logic?
Thanks for any pointers,
Nial