Simple question.. Is there anyway to set the altera maxplus2 synthesis tool to preserve a static hazard which has been deliberatly introduced?I cannot use a very high frequency clock but I do want a very short but not necceserily accurate output pulse using an xor and a string of LCELLs
Just select the WYSIWYG synthesis style in the ASSIGNMENT, LOGIC OPTIONS menu.
Yeah Ive tried that,it detects the static hazard,removes the static harard,which leaves the output stuck at '0' so it then removes the now redundant logic.Arrrrrrgh!!
ok, you can try to insert a LCELL primitive behind the redundant gates. Maxplus is not allowed to remove that if synthesis style is set to WYSIWYG.
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