Hi to everyone. I have some stupid problem that took lot of my time and if someone could help me please do so .I would be veryy greatfull
I was implementing counter for my fpga (vhdl)
and my code was thi
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is generic ( width: positive:=8); port ( CE: in std_logic; C: in std_logic; CLR: in std_logic; RST: in std_logic; Q: out std_logic_vector(width-1 downto 0); CEO: out std_logic; TC: out std_logic); end counter;
architecture Behavioral of counter is
constant TERMINAL_COUNT: std_logic_vector (width-1 downto 0) := (others=>'1'); signal Q_internal: std_logic_vector (width-1 downto 0); signal TC_internal: std_logic;
begin
process (CLR, C, CE, RST) begin if CLR = '1' then Q_internal '0'); elsif C'event and C='1' then if RST