Binary Counter Core

don't give me an option for generating Binary Counter even though I can find a

*.vhd file with component c_counter_binary... I have tried to integrate the counter manually, but Synthesiser can't find a library XilinxCoreLib (where this component is)... Help... Thank you

Which license files? Besides, even standalone CoreGEN does not have a binary counter in the list of it's cores I can only find it in the ISE Foundation files' folder. The funny thing is that folder XilinxCoreLib (it contains the counter) is in the same folder as IEEE but IEEE is recognised as a libray and XilinxCoreLib is not :-(.

First a question... why do you want to use CoreGEN to create a binary counter? That is a trivial thing to write in VHDL.

Normally, CoreGen embeds the path to the xilinxcorelib components into the cores that it creates, in a way that XST understands. If for some reason you actually wanted to use a XilinxCoreLib component separately (but in general you should not be doing this), you would need to add the library to your ISE project.

The XilinxCoreLib components are special, and I am not completely sure this will work, but here is how you normally add libraries to a project. Notice that in the ISE project window named "Sources in Project:", there is a tab at the bottom labelled "Library...". Right click and select "New Source". Select "VHDL Library" and name it xilinxcorelib. Make sure "Add to project" is selected and click on through to create the library. Then right click on the library, select "Add Source", and add the source code for the component. You want to select the *_comp.vhd version of the component, and hopefully XST will figure out that it is a xilinxcorelib component.

Hi all,

You don't need to add any library to the ISE project and you MUSTN'T include the vhdl file generated by coregen in you ISE project (is for simulation only is not synthetizable). Coregen generates edn file (eventually ngc file), that ise use during translate process. You must specify where are these files if you choose a special directory.

Regards.

Umm... perhaps you need to reread the original post, and my response. He specifically asked about using xilinxcorelib files without a Coregen generated edn file. And notice that my comment says "...(but in general you should not be doing this).

Umm.. perhaps you need to reread the original post. Vassili is talking about synthesis. Xilinxcorelib is only for simulation purposes. He just did it wrong.

Alain's answer is mostly correct! (The netlist format is edif, found in the *edn file) You correctly explained the flow for adding synthesis libraries to ISE projects. But never ever do that with Xilinxcorelib.

To Vassili: In the ISE 7In-Depth Tutorial vou find a chapter about using Coregen (p.

33). The example there uses the binary counter as well. The generated VHDL and verilog files are wrappers for the corelib instance and must only be added to a simulation project. In ISE 8.1 you can switch the sources window to different flows. In the synthesis flow view testbenches will not be displayed. In the simulation flows xco files will not be displayed, but the vhdl og verilog file of the core appear. For VHDL: a *.vho is generated which gives you an instantiation template for the generated core. The informations in this file have to be copyed correctly to the source where you want to instantiate the core (e.g. your toplevel design).

If you have generated the core in a separate folder you either have to copy the files to your ISE project folder or set the constraint for the macro paths correctly (for both, synthesis and implementation tools).

After generating the core you find a *_flist.txt file in your project directory like this for the example given in the ise7 tutorial:

# Output products list for tenths.edn tenths.vho tenths.vhd tenths.asy tenths.xco tenths.xcp tenths.sym

tenths.edn is the netlist file that will be used during implementation. tenths.vho contains the imstantiation template. tenths .vhd is the wrapper for simulation. tenths.asy and tenth.sym are symbols for schematic flows tenths.xco is the core information used by the project navigator. tenths.xcp ??? don't know, have to read the documentation.

About these license files: Vivek probably used a more complex core for which a license has to be bought separately. A lot of the simpler ones are for free and need no extra license.

Anyway, Vassili, better chage to ise8.1. The coregen is there integrated in the flow and works just fine. With *.xco files and everything.

have a nice synthesis Eilert

Thank you very much for helping me.

Unfortunately I still can't do it. I cant create instantiation template with ISE because it does not give such option and xst won't accpet mine instantiation template (when I'm trying to implement the design it gives me an error saying that it couldn't "resolve" this component). Has anyone used this counter at all?