What is the best way to move paralell bits of data over two clock domains inside an xilinx FPGA (Spartan-3E) to avoid meta stability?
By paralell bits i mean for example 10 x 16 bits of data collected from 10
16-bit AD converters in one clock domain which have to be moved to en different clock domain (of higher frequency).What about dual port RAM, are they safe?
Or should i clock all data individually through two d-flipflops in series which are clocked by the second clock?