Avnet Virtex-4 FX12 mini module

All the GbE PHYs I have seen have their datasheets available only under NDA.

If the sources for the ML-401 demos (IIRC, there was a networking demo in there) are available, you could look around in there to find the PHY's initialization sequence.

Alternately, I presume GbE PHYs belong to a finite number of families (MII for example) so you might be able to get baseline functionality by reading those generic PHY interfaces' specs.

Just one datapoint here: We are using an AVnet board with a National Semiconductor DP83861 10/100/1000 Ethernet PHY on it and the datasheet is available for download from their homepage. So there are PHYs with public documentation available.

/Andreas

Ok. I will try to get the data sheet this way. In the meantime, can you suggest the easiest way of establishing the Gigabit etherner connectivity between the FPGA and the host PC. I need speed in excess of 50 Megabytes / Sec. Should I go the EDk way or to try the verilog side. I have Virtex-4 FX so it has extensive support for Gigabit ethernet. Thanks.

It depends on what kind of application/data we are talking about. It is for example not that hard to send UDP data to a static IP address using a hardcoded MAC address in your design. The dataflow could be something like the following:

Data in --> FIFO --> Add UDP/IP header --> Asynchronous FIFO -->

--> CRC generator --> Ethernet PHY

This setup should work well if you have a fast PC connected to your design either directly or through a switch. However, you should be prepared to lose a few packets here if your PC is not fast enough or does not allocate enough buffer space for UDP packets coming in at 50 MB/s. However, if you need something like TCP/IP or the ability to buffer data in an off-chip memory and send it to the PC on demand, you are facing a tougher problem. In this case it is probably worth to investigate what the EDK has to offer.

If you are going the first route I would suggest that you look at the following lab exercise which has some good information (only for

10/100 Mb/s Ethernet but the only difference is that you are typically using 8 wires for data to a gigabit Ethernet PHY instead of 4):

and

In particular, they have an explanation of the Ethernet CRC and a couple of example CRC:s which is very valuable when you are trying to send an Ethernet packet through your own CRC generator.

/Andreas

Don't forget to check out XAPP's 434 and 443:

The reference designs here might be just what you are looking for.