1250gbps input on virtex-5

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we need to input a continous stream of 32 LVDS data bits at 1.25gbps
per pin into a Virtex-5.
There is a clock provided for each byte (source synchronous).

There was a news item by Xilinx that says this is possible. But how
many loops do I need
to jump through to make it work?

- What speedgrade do we need?
- Is there a difference in timing between LXT, FXT and SXT for LVDS
- Are there any constraints regarding the placement of the pins?

Has anyone in this group done speeds like this before?


Kolja Sulimma

Re: 1250gbps input on virtex-5

I suggest you work with your FAE.

It is challenging (for the signal integrity alone, not even considering
the FPGA).

The V5 has serdes capability built in per pin (pair), so this is what
gets used (the fabric doesn't have to run this fast -- it can not).

LXT, SXT, FXT all have identical LVDS.  Speed grade does no apply to
LVDS (they are all graded the same).  How the design is done will
determine what speed grade is required.

I suspect you meant "how many hoops do I have to jump through" (not loops).

I do not have an answer for you, other than people are doing this sort
of thing.


Kolja Sulimma wrote:
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Re: 1250gbps input on virtex-5
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Kolja, there is a very good app note (43 pages long) that describes
the design, and its dynamic alignment in gory detail.
This is all based on actual testing of Virtex-5 chips on our
evaluation board. Greg Burton, the applications engineer, drove the
design all the way to 1.4 GHz, where the eye got very small.(see page
Good luck with your design, you are in good hands with this app note,


Peter Alfke

Re: 1250gbps input on virtex-5
Thx. That is exactly what I was looking for. (Actually I need XAPP860)
As I read this we have multiple options:
- use a -3 speedgrade
- use a power supply 5% over nominal voltage with extremely good
- rely on the fact that the signal quality will be better than what is
used in the application note.

We probably will choose all three options at once. :-)
Are -3 devices available? Our distributor could not give us a quote.


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Re: 1250gbps input on virtex-5
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Hi Kolja,
Indeed, XAPP860 is a big improvement. In fact, it strikes me that with a
little work, an initial Rx cal with a training pattern isn't necessary for
eye alignment and the V5 can dynamically align to random data by comparing
the outputs of the master and slave ISERDES. Word alignment could be
achieved by looking for known patterns in the incoming signal, e.g. F628 for
Cheers, Syms.

Re: 1250gbps input on virtex-5
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Kolja, I should have referred you to the XAPP860. My oversight...
Regarding -3 devices, they do exist for all the smaller part types,
but not for the largest ( '200 and above).
-2 might be good enough for your application. -3 has a faster clock
distribution, but there is little (if any) difference in the LVDS and
ISERDES structures.

Re: 1250gbps input on virtex-5

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Easy enough. The application notes link to each other.

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At those speeds 100ps make a big difference. The application notes
that at 1200Mbps the sampling windows is twice as large on a -3 than
it is
on a -2 device.
However, it really seems to be the case that -2 is good enough.
as we can run the device easily at +3% supplies.

Thank you for the pointer,


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