Until now, I thought that superscalar processor design is only of interest for the desktop computer. However, since more and more transistors can be packed on the same die, I am wondering if there are now already the first superscalar processors available for the embedded market? Or are they not suitable because of the power they consume?
Have been for a while now. The Toshiba MeP with IVC2, for example, can run up to 3 different insns per cycle, and the MN10300 has some dual-opcode encodings for two insns per cycle. IIRC many TI DSP chips run multiple insns per cycle also.
The Wikipedia page on Superscalar notes that there was a superscalar i960 variant back in 1990.
Far from first, some have been around for many years. The power architecture (used to be known as PPC) from Freescale offers a huge variety of choices and sizes, I believe AMCC make and develop what used to be the embedded line of PPC processors IBM used to make. I guess even Microchip are there now with their PIC32, it has a MIPS core which probably is that as well (but I am not quite sure, never investigated it really).
I can't see any reason why a switch to superscalar would be related to a switch to 64 bits.
One issue with superscalar for embedded use is that it tends to make timings less predictable, although I'm not sure how relevant this is on a 32-bit system.
I can't see any naming coherence with Microchip's products, except PIC32. PIC10F : 12 bits per instruction PIC12F : 12 OR 14 bits (depending on... never mind.) PIC16 : 14-bit instruction words PIC30, PIC33 : WTF ? Who knows what their marketing department will invent next time ?
However I have to show respect to their technical team who seems to have done a lot of good initial choices, starting with a MIPS core instead of yet-another-ARM-implementation. But I can't say if these good ideas turned into a good implementation, I had bought the kit but never found the time to use it and the manuals and software are... huh... disproportionaly big. Hence my further investments in YASEP.
Depends. LIW-based architectures are pretty predictable. Some DSP architectures today fit this description. And yes, predictability is not always a goal if raw performance is the target. I've seen at least 1 DSP family play that game... but I have no idea if it has had any success because I don't see it mentioned since its release.
yg
PS : OT but
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is updated with more pictures and actual measurements :-)
For embedded application you can choose MCUs with on-chip flash or MPUs with large external Flash/RAM space.
Renesas offers their SH2A Superscalar cores in both variants (720x and 726x parts). This is an MMU-less core that can run 2 instructions per cycle. When using an FPU it can do even more!
A good example is the 7216:
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(There's even a dual-core variant available that gives 4 instructions per cycle.)
The SH4A is the MPU version with MMU that uses external memory. It runs Linux and WinCE. It is also available in a dual-core.
A good example is the 7764:
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