problem using SSI1 port on Cirrus logics EP7312.

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One of my friends asked me to try to collect some intelligence on this
phenomenon: he tries to interface an SPI real-time-clock IC (Rx5C348 /) to a Maverick EP7312 CPU
using its SSI1 port. The communication works OK except for the fact that
data gets shifted one bit both on reception and transmission. This means
that the LSB cannot be set or retrieved from any of the registers of the
clock IC. He examined the communication with a logic analyzer and says that
the wires already contain the shifted data and that the CPU 'swallows' the
first bits of the communication.

Does anyone have any experience in this field? What could be the problem?

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