Coolrunner 2 CPLD IO

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Hi,

Taking advantage of a good exchange rate to the USA at present, I bought
a coolrunner 2 CPLD evaluation kit from xilinx.  I didn't check the IO
standards of the supplied device though.  I've now found it uses LVTTL
amongst other things.

The top end voltages of LVTTL is about mid range on standard bipolar TTL
and in the linear area of CMOS.  Does anyone have any experience of
interfacing these three differing IO standards?

I really want to interface to standard ROM / RAM, a z80 and RS232, is
there a cheap easy fix for this ?

Next time I read the datasheet!

cheers,
Dave

Re: Coolrunner 2 CPLD IO
Hi, yes this lower voltage is a pain and is going to get worse.

Re: Coolrunner 2 CPLD IO

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  It's not as bad as you might think.
Newest lower voltage uC are offering 5V compatible IO, and the
newest Lattice 4000 family, also have 5V compatible IO, as do
the better LV logic families.

  Customers are demanding it, because besides legacy interfaces, some
devices like PowerMOSFETS are not following the Vcc's down, so
5V drive is important for them.
  CORE voltage will trend downwards, but it is only design laziness
that also trends down the IO specs. It just takes more effort, and a
tiny amount more silicon, to give 5V compatible IO.

  The 3.3V CR II will drive TTL which includes RAM.EPROM and RS232
driver devices. You do need to watch HCMOS overdriving the CR
inputs, and any 4000 series CMOS devices as loads.

-jg


Re: Coolrunner 2 CPLD IO

: > Hi, yes this lower voltage is a pain and is going to get worse.

:   It's not as bad as you might think.
: Newest lower voltage uC are offering 5V compatible IO, and the
: newest Lattice 4000 family, also have 5V compatible IO, as do
: the better LV logic families.

:   Customers are demanding it, because besides legacy interfaces, some
: devices like PowerMOSFETS are not following the Vcc's down, so
: 5V drive is important for them.
:   CORE voltage will trend downwards, but it is only design laziness
: that also trends down the IO specs. It just takes more effort, and a
: tiny amount more silicon, to give 5V compatible IO.

:   The 3.3V CR II will drive TTL which includes RAM.EPROM and RS232
: driver devices. You do need to watch HCMOS overdriving the CR
: inputs, and any 4000 series CMOS devices as loads.

5 Volt static CMOS devices will nedd higher current standby current, as the
input buffers will carry some currents, as both P and N transistor are
partial switched on.

--
Uwe Bonnes                 snipped-for-privacy@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Re: Coolrunner 2 CPLD IO

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Is there something wrong with 3.3 V CMOS? That should interface
rather nicely to 5 V TTL. The problems start when you try to interface
to 5 V CMOS, then the voltage is too low.

- Ville

--
Ville Voipio, Dr.Tech., M.Sc. (EE)

Re: Coolrunner 2 CPLD IO
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I agree this is fine for 3.3V CMOS, I want to interface to a mixture of
standard CMOS and TTL though.

Just wondering if the is a cheap and easy way to do this that will not
fry the CPLD.

The designs I have planned will probably never go above 4 MHz, so there
is no problem if the quick fix craps out at speeds much greater than
this.

cheers,
Dave

Re: Coolrunner 2 CPLD IO
snipped-for-privacy@webshed.org says...

Thanks for all the comments, I think I have got it all going ok now.  
Nothing has let the magic smoke out yet anyway...

cheers,
Dave

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