Hey all--
So my experience with the native bitstream compression algorithms provided by the FPGA vendors has been that they don't actually achieve all that much compression. This makes sense given that the expansion has to be accomplished in the FPGA hardware, and so can't be all that aggressive.
I generally find myself programming FPGAs from microcontrollers, and so I've got clock cycles and RAM to throw at the problem to try to do better. We've had some limited luck implementing really stupid RLE, just compressing the runs of 0x00 and 0xFF and calling it a day. But I was wondering whether anyone's found a better, more universal approach.
The ideal would be a compression/expansion library with fairly good compression ratios, where the expansion side could operate without malloc and on-the-fly on a stream of data rather than requiring large buffers. The compression side could use phenominal amounts of compute power and RAM, since it would be happening on the PC. But the goal would be able to decompress on something like an LPC1754 (32kB RAM total).
Anyone have any thoughts?