AT91SAM7S Performance

Hi everyone,

I would like to know how could be calculated the performance for the AT91SAM7S micros.

I have my system running @ 48 MHz (MCK), but when I measure the instruction execution time in very slower. Ho do the pipeline and others factors change the mips value?

Thanks, Karl

Reply to
Karl Ernst
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"Karl Ernst" skrev i meddelandet news:Esydnau3Bp5V_ZrUnZ2dnUVZ snipped-for-privacy@giganews.com...

The flash will run at ~33 MHz so you have to have at least one waitstate. (You can with some care, overclock to 48 MHz zero waitstate if the temperature is not too high)

At 1 waitstate, the CPU performance in ARM mode will drop from

0,9 MIPS/MHz to 0,45 MIPS/MHz, because all instruction fetches will take two clock cycles. . The CPU performance in Thumb mode will not drop as much, because, even though the CPU fetches 16 bit instruction, the flash memory controller will fetch 32 bit, so you will see mostly zero waitstate from the flash. You will see one waitstate on non-sequential fetches and datafetches. In Thumb mode, the performance is 0,79 Dhrystone MIPS/MHz at zero waitstate, but since you only see waitstates on parts of the fetches, you will see much less degradation (unless the libraries are compiled for ARM mode of course)

Data access will directly affect performance since the instructions and data are fetched over the same bus,and any data access may reduce the instruction bandwidth.

The way to get performance of the SAM7 is to compile most code for Thumb mode, but critical sections should run in ARM mode, executing from SRAM at zero waitstate.

If you do not want to mess around, you can always use an AT32UC3B instead. This will run at 60 MHz, due to its dual PLL, and should have an equivalent price. Since the AVR32 does 1,25 MIPS/MHz with 1 waitstate, you will have much better bang for the buck.

--
Best Regards,
Ulf Samuelsson
ulf@a-t-m-e-l.com
This message is intended to be my own personal view and it
may or may not be shared by my employer Atmel Nordic AB
Reply to
Ulf Samuelsson

That's obviously impossible, because no such thing as "the" performance exists. Performance of a micro in a particular application depends at least as much on that application, and the way it was implemented, as it does on the microprocessor itself.

Which instruction time is that? How did you measure it? And it came out slower ... than what?

Short answer: if they change it, they change it. For the long answer, read the datasheets. All of them applying to that particular micro, that is.

Reply to
Hans-Bernhard Bröker

On Wed, 29 Oct 2008 04:26:46 -0800, Hans-Bernhard Bröker wrote (in article ):

Tremendous help! Can I quote you for an article on optimizing small ARM systems?

-- Charlie Springer

Reply to
Charlie Springer

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