Hi,
I'm trying to implement (in spice) some small circuits I've seen in lectures. I'm hoping that someone can confirm my thinking, with regards to biasing and feedback.
I've got a basic nmos inverter with pmos load, and I'm generating the bias for the pmos transistor by mirroring it off a reference, as shown here:
The W/L ratios of the transistors are: M1,M2=(129/5) and M3=11/1.
At the moment, I'm only interested in biasing the circuit up, so I just stuck a 1V DC source onto the input of M3. However, the circuit didn't quite work - the drain current through M2/M3 was only about 85uA and M2 had dropped out of saturation - the voltage at node 4 was 2.93V (so for M2, Vds=-0.37V, but Vgs-Vt was -0.404V).
After a bit of reading and thinking, I suspected that the voltage at node 4 was not well defined, so I used a VCVS with gain 1 to feedback the output node voltage to the input (node 5). This sorted out my problem - I got 100uA down Id2/id3 and all transistors stayed in saturation.
So is this the right thing to do? In lectures we considered only the two transistors M2 and M3 and ignored biasing conditions (ie. just looked at the AC performance of the circuit). They didn't mention feedback... is it required?
Cheers,
Ted