This has two of the tiny EPC BGA GaN fets and a gate driver. It can be used as a throw-away component on other boards.
This is the dual-fet high-current version of the thing I posted a while back. The fets are in parallel but the drains come out to separate mouse-bites and test points so we can test everything properly.
Here's the test fixture.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
John Larkin
The question is: 'What happens when there are more holes than matter'
2 resistors? 1 390 Ohm (drain I suppose) the other one hard to tell, 470 maybe.Missing : circuit diagram.
Real gold detected!
LOL
I would just use a piece of 10 cent veroboard, as the long wires and high resistor values give away it is not really RF?
+5 not decoupled close to ground.Is it a curve tracer?
????
vero doesn't have the heat transfer
NT
wrote in news:ppk6an$1vqi$ snipped-for-privacy@gioia.aioe.org:
The answer is: One gets better heat transfer numbers.
That is an idea for a polymer board though.
Take gold rivets (FLOABW), and make the interconnections with gold wire, then 3D print the PCB over the rivet/wire assembly. No more fiberglass. There would be applications for this. It is like when one pots the HV section of an HVPS, but more precise and more planar.
Is that the same size as a 8-pin DIP? That's a cute idea.
George H.
On a sunny day (Wed, 10 Oct 2018 02:39:00 -0700 (PDT)) it happened snipped-for-privacy@gmail.com wrote in :
Heat transfer from 5V in a 390 Ohm resistor????
Ya musta beee kidding
No, the size is pretty arbitrary. But it does surface-mount onto some larger board. Those tiny fets will be glob-topped, and that makes rework even more impossible, so we put the fets on a disposable subassembly.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
The GaN fets are tiny and will get hot. The board is 32 mils thick and
2 oz copper on both sides, and the vias help spread the heat.At a given current, two fets in parallel result in less than 1/4 the dissipation per fet compared to using one.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
I've no idea what you mean there
NT
This is my hack for testing the dual-fet board:
This will work for the old single-fet version too.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
John Larkin wrote
OK, that will give rise-time depending on circuit wiring - and scope lead capacitance I suppose. If you were to drive it with a ramp on one scope channel, it could give the pinch of point / transfer.
I don't know this transistor, suppose it is very fast, the chip on that mouse byte board only shows 'LXE'
I have some Sirenza VCOs that use a similar mouse byte PCB, have not had any problems with that in prototyping
Been coding a Linux test program for the LMX2332 PLL chip, very hard to read datasheet, could not register on TI site to download their windows program, so writing my own.
What could have been done in 10 lines in that datasheet, is done over many pages with bit numbers in reverse, starting bytes at bit 1, not 0, and all sort of other strange things. Maybe made by some intern or something, maybe same person did their website..
It strongly reminded me of than bomb defusing manual
1) turn big screw 180 degrees left. 2) before you do that pull pin out of hole. 3)Made some test cable for testing via PC par port, and got some parts together to test and build that LMX2332 based board.
I am writing code in C on the PC and test that chip, then will rewrite it in PIC asm for the on-board PIC. At least that is the plan. If the C program works as I hope, then I will release it open source so people are freed from that TI windows stuff. Will be a command line tool though, its simple enough not to need any graphics. if you can figure out that datasheet that is:
We had to develop c code to drive the LMX2571 synth chip. It has a 62 page data sheet and about 4000 registers, and involves all sorts of rules and number-theory stuff.
TI wasn't any help. They obviously have procedures to go from frequency to register settings, and they obviously have c code in their eval kits, and they refused to let us see any of that.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
John Larkin wrote
I have the software framework running now, hard to find test vectors, but one thing bugs me in this chip: there is one output pin that seems multiplexed to show different signals in the chip, like outputs from different dividers etc... But in the control registers you can set bits that connect more than one signal at the same time to that pin.
So in theory it seems you can destroy the chip by sending the wrong config data. That is very bad chip design IMO.
Maybe there is some protection, but then the datasheet is wrong. So I added a software abort in case the wrong bits are set.
There have been some chips, like FPGAs, that could literally be fried by software mis-configuration, but that's very rare. If the mux is mis-programmed, it's unlikely that any damage would be done.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
John Larkin wrote
Yes, the FPGA oscillating over a few gates really heats it up, causes hot spots! Been there, done that, but it did survive.
In the LMX2332 datasheet I do not see any power on states of the configuration registers specified either. Better have a current limiting resistor in the supply I think...
Xilinx had a generation of chips that used internal tri-state busses for signal routing. You could do a design that turned on all the tri-state buffers, some high and some low, and draw lots of amps. If the power supplies held up, that would melt the chip.
They also had some that could be damaged if powerup dV/dT wasn't right.
Our LMX2571s are working beautifully. That functionality would have been a rack full of gear, worth some good chunk of a magabuck, not that long ago. The jitter levels are amazing.
But the driver and the math were a real pain. We had to do the repeated-fraction thing to get the optimum (N/M)/K to best hit a desired frequency. Brute force, it might be a week of computing.
TI should supply some sample code. I can't imagine why they don't. It probably costs them sales.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
John Larkin wrote
In my case it is not all that critical, divide 10 MHz Rubidium by 10 to 1 MHz, divide 24 MHz or 25 MHz VCXO by 24 or 25 to get 1 MHz, compare those in phase detector, steer the 25 MHz or 24 MHz VCXOs. Output 24 or 25 MHz with Rubidium stability. The 24 MHz will be multiplied in the LNB by 390 to 9360 MHz, and used to mix down the 10.4 GHz satellite signal. The 25 MHz will be multiplied by 390 or 426 for use as LO for normal satellite reception. That is the plan anyways. Nothing happened today, was working in the garden...
Too many possibilities I guess.. But indeed some examples do help. Could use that to verify my program.
If all else fails I was sort of thinking I can use a PIC (build in counters). I have a quite accurate PIC frequency counter in a D connector:
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