Clock Input to ADC

It would need to be a very hgh speed comparator. The obvious candidate would be the Linear Technology LT1016, but it doesn't look as if it will do better than 25MHz.

There are faster comparators around - the original Advanced Micro Devices Am685 could handle 100MHz back in 1972, and its many successors have become progressively faster. The Analog Devices AD96685 comes to mind - we used a bunch of them at Cambridge Instruments in the late

1980s. Analog Devices now sells even faster parts - their web site threw up the ADCMP582BCP-RL7 which is made on a silicon-germanium process, and they are not the only game in town.

Sadly, these faster parts produce an ECL compatible output. This is easy enough to transform into a +/-5V square wave or triangle wave with discrete transistors - back in the late 1980s at Cambridge Instruments we did this with 5GHz wideband transistors like the BFR92 (NPN) and the BFT93 (PNP) which are still ex-stock parts from Farnell.

Using these sorts of parts does take some care - you need to put around

33R of "base-stopping" resistance close to every base input, otherwise the transistors are prone to oscillate, and the circuit should be laid out on the basis that interconnections are terminated transmission lines, running over a solid ground plane - but it is perfectly practical.

Getting a good +/-5V sine wave out of the output could be trickier - the obvious solution is to use a multi-pole low pass filter to clean the higher harmonics out of the triangular wave. The harmonic content of the triangular wave is already relativiely low, because their amplitude decreases as the square of the harmonic number, so it doesn't take much filtering to get rid of the hgher harmonics, but you might need a multipole filter to get acceptable attenuation of the third harmonic. If your original square wave has an exactly 50% duty cycle, there won't be any even harmonics.

-------------- Bill Sloman, Nijmegen

The ADC is a high-speed data acquisition card from exacq technologies (CH-3160). The clock input on the CH-3160 is a high impedance input ~10kohm. By writing to a register I can set the boards internal clock comparator threshold to 0V or 1V. The clock input signal should be limited to +/- 5V.

I currently have the comparator threshold set to 1 V. My current clock driver board is taking an external 66Mhz PECL clock and level shifting to 5V ttl and driving a 50 ohm cable about 5 feet. I then terminate the cable with a 50-ohm load at the CH-3160 clock input. With this setup the CH-3160 sees an unstable clock in the form of glitches and/or missed clock pulses.

I believe the problem is caused by the fact that the spec for ttl is

0.8V for a low level (very close to the 1V comparator threshold), and the fact that ttl drivers typically have asymmetrical drive impedance not allowing me to terminate the 50 ohm cable correctly to give a pretty waveform at the ADC board end.

I figured the quick and dirty solution would be to AC couple the 5V ttl signal, which would only require a capacitor in series with the 50-ohm cable and ADC clock input.

You're confused- you show me an A/D that requires 10Vpp clock at 66MHz. Go back to the datasheet for your A/D and read the application examples, they will show you how to drive the clock there. If you are unable to do that, then what makes you think you can understand anything anyone tells you on USENET. You're probably dealing with a differential CLK-/CLK .

No, the error was is giving the TTL to a

50 Ohm cable. TTL never drives 50 Ohms. Use the PECL for that and it'll work.

Rene

--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

I've read over the posts so far. Your glitches are most likely caused by ringing at the load.

I would suggest that you try AC coupling with no other conversion, and set the threshold to 0V. Keep the shunt terminator on the load. Make sure that you calculate an appropriate C for the AC coupling.

You may also want to source terminate your driver with a series R of around 22 Ohms, if that is possible. The idea is to estimate the source resistance of the driver, and then add whatever you need to bring it up to

50 Ohms. The datasheet may give you enough information to calculate a typical source resistance.

The most important thing with clocks is monotonic rising and falling edges. How does this clock look when you feed it to an oscilloscope with a

50-Ohm termination?

Oh, also, this clock never stops, does it? It would be disastrous because the 50-Ohm termination would keep the input right at the switching threshold.

--Mac

That +/-5V limit is probably a damage limit, and it is definitely not a recommended signal level. The 0V threshold is the ideal for an AC coupled input symmetrical about GND, and the intermediate levels up to

1V would be for a unipolar input clock input. You have a few quick and easy options here. Since you say the external 66MHz is PECL, which strictly interpreted means it is riding on a DC bias of ~3.7V, you can relay it through to the ADC with a PECL dvr like so, set the threshold to 0V: View in a fixed-width font such as Courier.

. . . . 0.01u . PECL>-+----||--->>--------->>-+-> ADC . | ----+---- | . [270] | [50] . | | | . +---------------+-------+ . --- --- . gnd gnd . .

Going with TTL you can do this- omit the termination at ADC end:

View in a fixed-width font such as Courier.

. . . . TTL DVR . . |\\ 0.01U . | >--[Rx]-+-||--->>---------->>--> ADC 10K IN . |/| | ----+---- . | | | THRESHOLD=0V . | [100] | . | | | 0.8Vpp . | | | . +-------+------------+-----------+ . | | . gnd gnd . . . . select Rx for best response . . where (Rx+Rd)||100~50 ohms on average . . Rd= average driver output impedance . . start w/ Rx=68,75,82 ohm sequence etc... . . . . Also parallel drivers lessens asymmetry in Rd: . . . TTL DVRs . . . |\\ . +----| >--[Ry]-+ . | |/ | etc Ry=N x 100 ohms -Rd . | | . | |\\ | N= # dvrs in parallel . >---+----| >--[Ry]-+ . | |/ | . | | . | |\\ |0.01U . +----| >--[Ry]-+-||--->

. |/| | . | | . | [100] . | | . | | . +-------+------- . | . gnd .