I tried simulating a transmission line transformer (one end connected in parallel, the other end in series) using "CircuitMaker 2000" and "MultiSim 8", but apparently the models these programs use (even the lossy line model) are not appropriate for this type of simulation.
I'm wondering, does anyone know of software that will realistically simulate such transmission line based circuits in the time domain? Thank you.
I have been working up a spice model of a transmission line transformer that approximates it with 16 inductances and 17 capacitances. It was meant to model a transformer wound through two flat cable cores, so that the winding pair runs straight down the slots, with the ends as far as possible from each other. It includes the 120 mutual inductance coupling factors that model the reduction of coupling efficiency as turns get further apart and both the normal transmission line capacitance per length and the capacitance between 1 turn and the next of the pair. The responses have not been tested against actual measurements, but they look quite reasonable, as long as the phase shift per inductance segment is a small part of a cycle.
I selected the inductance and capacitance values to fit test data on a particular example, but you can change them.
I built it for LTspice, free download at:
If you would like to have a copy of this component model and its symbol file, email me.
A long string of L's and C's makes a good transmission line model, but the number of sections explodes as a power of the delay/risetime ratio. I've done lines with hundreds of sections.
Most Spice transmission line models contain a hidden isolation transformer (you can apply DC between the 'shields' of opposite ends) and aren't very realistic for things like transmission-line transformers.
John
John,
In SPICE-speak, the transmission line device of SPICE handles a single node. A length of coax has two nodes, normal mode and common mode. To invert, you need to model both modes. The classic example is in Larry Nagel's PhD thesis(Berkeley 1975), but here's a deck that will show how to do a transmission line inverter in LTspice on the netlist level:
The general case is that a cable has as many modes as conductors including the shield. That the SPICE transmission line device supplies only a single node is an odd concept to be sure -- a cable with but a single wire but controlled impedance. Just the same, it's supper useful if you ground each end of one of the sides. Then you can simulate the normal mode and skip the common mode if it doesn't interest you.
--Mike
This is a super-wideband inverter, in both Spice and real life:
(----------------) in+ ----( coax )----(---------------) in- ----(----------------)----( coax )------ out+ (---------------)------ out-
The Spice version is perfect. The real version has problems if IN- and OUT- are both grounded (the whole thing becomes a short) and that limits low-frequency response. Slipping a ferrite over it somewhere helps the lf end a lot. The center crossover should be zero-length. Done with a couple of hunks of hardline, it's very impressive.
John
John,
Interesting example. Thanks.
But it doesn't work very in SPICE if you dutifully model both modes of each cable. Your circuit above requires four SPICE transmission line elements. Yes, if you ignore two propagation modes, it's perfect in SPICE but that is an error in the application of SPICE. Below is an LTspice schematic that illustrates perfect behavior from incorrect analysis and the results from using 4 ideal propagation modes.
Regards,
--Mike
--- xmissionbs.asc ---
Version 4 SHEET 1 880 680 WIRE -240 208 -240 -96 WIRE -240 272 -240 208 WIRE -240 400 -240 352 WIRE -160 -96 -240 -96 WIRE -160 208 -240 208 WIRE 16 -16 -80 -16 WIRE 16 -16 16 -64 WIRE 16 16 16 -16 WIRE 16 96 16 48 WIRE 48 272 -48 272 WIRE 48 272 48 240 WIRE 48 288 48 272 WIRE 64 -96 -80 -96 WIRE 64 -64 16 -64 WIRE 64 16 16 16 WIRE 64 48 16 48 WIRE 96 208 -80 208 WIRE 96 240 48 240 WIRE 208 -64 160 -64 WIRE 208 -16 208 -64 WIRE 208 16 160 16 WIRE 208 16 208 -16 WIRE 208 48 160 48 WIRE 208 96 208 48 WIRE 240 -96 160 -96 WIRE 240 -16 208 -16 WIRE 240 240 192 240 WIRE 240 288 240 240 WIRE 256 208 192 208 WIRE 256 240 240 240 WIRE 288 208 256 240 WIRE 288 240 256 208 WIRE 304 -96 240 -16 WIRE 304 -16 240 -96 WIRE 336 -16 304 -16 WIRE 336 -16 336 -64 WIRE 336 16 336 -16 WIRE 336 96 336 48 WIRE 352 208 288 208 WIRE 352 240 288 240 WIRE 384 -96 304 -96 WIRE 384 -64 336 -64 WIRE 384 16 336 16 WIRE 384 48 336 48 WIRE 496 240 448 240 WIRE 496 288 496 240 WIRE 528 -64 480 -64 WIRE 528 -16 528 -64 WIRE 528 16 480 16 WIRE 528 16 528 -16 WIRE 528 48 480 48 WIRE 528 96 528 48 WIRE 560 208 448 208 WIRE 576 288 496 288 WIRE 608 -96 480 -96 WIRE 768 -16 528 -16 FLAG 48 288 0 FLAG 240 288 0 FLAG -240 400 0 FLAG -48 272 0 FLAG 560 208 0 FLAG 16 96 0 FLAG 208 96 0 FLAG -80 -16 0 FLAG 336 96 0 FLAG 528 96 0 FLAG 608 -96 0 SYMBOL tline 144 224 R0 WINDOW 3 -76 43 Left 0 SYMATTR Value Td=70n Z0=50 SYMATTR InstName T1 SYMBOL voltage -240 256 R0 WINDOW 123 0 0 Left 0 WINDOW 39 24 132 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 1 0 1n 1n 10n) SYMBOL tline 400 224 R0 WINDOW 3 -76 43 Left 0 SYMATTR Value Td=70n Z0=50 SYMATTR InstName T3 SYMBOL tline 112 -80 R0 WINDOW 3 -76 43 Left 0 SYMATTR Value Td=70n Z0=50 SYMATTR InstName T2 SYMBOL tline 112 32 R0 WINDOW 3 -76 43 Left 0 SYMATTR Value Td=50n Z0=75 SYMATTR InstName T4 SYMBOL tline 432 -80 R0 WINDOW 3 -76 43 Left 0 SYMATTR Value Td=70n Z0=50 SYMATTR InstName T5 SYMBOL tline 432 32 R0 WINDOW 3 -76 43 Left 0 SYMATTR Value Td=50n Z0=75 SYMATTR InstName T6 SYMBOL res -64 192 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 50 SYMBOL res -64 -112 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R2 SYMATTR Value 50 TEXT 288 352 Left 0 !.tran 0 500n 0 1n TEXT -16 208 Bottom 0 ;IN+ TEXT -16 272 Bottom 0 ;IN- TEXT 528 208 Bottom 0 ;OUT- TEXT 536 288 Bottom 0 ;OUT+ TEXT -48 -96 Bottom 0 ;IN+ TEXT -48 -16 Bottom 0 ;IN- TEXT 560 -96 Bottom 0 ;OUT- TEXT 568 -16 Bottom 0 ;OUT+ TEXT 272 -104 Bottom 0 ;"Correct" TEXT 272 176 Bottom 0 ;"Incorrect"
The actual arrangement sure works a whole lot better than your "correct" SPICE model!
I obtained a fair match to reality by modelling a transmission line transformer as a tline with both screen terminals connected together, followed by a pair of coupled coils wired as a balun. The tline acounts for delay effects and the balun for imperfect coupling and common mode currents. For an example, see:
Regards, Jeroen Belleman
I'll post some scope pics to a.b.s.e. Interestingly, "outside mode" impedance doesn't seem to matter. In fact, squeezing the coax close to the crossover improves the waveforms a bit.
When Spice conflicts with reality, where's the error?
John
In the model.
...Jim Thompson
-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |
The lack of Dark Matter in spice?
martin
John,
Opps, The schematic I posted has the outputs incorrectly connected. Below is a revised schematic. It becomes an ideal inverter as the current in the shield in driven to zero.
The thing I'm trying to point out is what the SPICE transmission line element is doing -- a single mode. To do a transmission line inverter, you need two modes or two transmission line elements as in the 1st netlist I posted. The other mode results in the field that is external to the cable and will be more problematic to model. In Larry Nagel's Ph.D. thesis, he just assumed it was faster propagating and higher-Z, as if the thing were in open air.
It's a common error to think that the transmission line element element is intended to model some lenght of coax.
If you have field outside of the cable(your clue is that the ferrite outside the cable helps), you'll best model both modes of propagation.
--Mike
Version 4 SHEET 1 880 680 WIRE -240 208 -240 -96 WIRE -240 272 -240 208 WIRE -240 400 -240 352 WIRE -160 -96 -240 -96 WIRE -160 208 -240 208 WIRE 16 -16 -80 -16 WIRE 16 -16 16 -64 WIRE 16 16 16 -16 WIRE 16 96 16 48 WIRE 48 272 -48 272 WIRE 48 272 48 240 WIRE 48 288 48 272 WIRE 64 -96 -80 -96 WIRE 64 -64 16 -64 WIRE 64 16 16 16 WIRE 64 48 16 48 WIRE 96 208 -80 208 WIRE 96 240 48 240 WIRE 208 -64 160 -64 WIRE 208 -16 208 -64 WIRE 208 16 160 16 WIRE 208 16 208 -16 WIRE 208 48 160 48 WIRE 208 96 208 48 WIRE 240 -96 160 -96 WIRE 240 -16 208 -16 WIRE 240 240 192 240 WIRE 240 288 240 240 WIRE 256 208 192 208 WIRE 256 240 240 240 WIRE 288 208 256 240 WIRE 288 240 256 208 WIRE 304 -96 240 -16 WIRE 304 -16 240 -96 WIRE 336 -16 304 -16 WIRE 336 -16 336 -64 WIRE 336 16 336 -16 WIRE 336 96 336 48 WIRE 352 208 288 208 WIRE 352 240 288 240 WIRE 384 -96 304 -96 WIRE 384 -64 336 -64 WIRE 384 16 336 16 WIRE 384 48 336 48 WIRE 496 240 448 240 WIRE 496 288 496 240 WIRE 528 -64 480 -64 WIRE 528 -16 528 -64 WIRE 528 16 480 16 WIRE 528 16 528 -16 WIRE 528 48 480 48 WIRE 528 96 528 48 WIRE 560 208 448 208 WIRE 576 288 496 288 WIRE 608 -96 480 -96 WIRE 768 -16 528 -16 FLAG 48 288 0 FLAG 240 288 0 FLAG -240 400 0 FLAG -48 272 0 FLAG 560 208 0 FLAG 16 96 0 FLAG 208 96 0 FLAG -80 -16 0 FLAG 336 96 0 FLAG 528 96 0 FLAG 608 -96 0 SYMBOL tline 144 224 R0 WINDOW 3 -76 43 Left 0 SYMATTR Value Td=70n Z0=50 SYMATTR InstName T1 SYMBOL voltage -240 256 R0 WINDOW 123 0 0 Left 0 WINDOW 39 24 132 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 1 0 1n 1n 10n) SYMBOL tline 400 224 R0 WINDOW 3 -76 43 Left 0 SYMATTR Value Td=70n Z0=50 SYMATTR InstName T3 SYMBOL tline 112 -80 R0 WINDOW 3 -76 43 Left 0 SYMATTR Value Td=70n Z0=50 SYMATTR InstName T2 SYMBOL tline 112 32 R0 WINDOW 3 -76 43 Left 0 SYMATTR Value Td=50n Z0=75 SYMATTR InstName T4 SYMBOL tline 432 -80 R0 WINDOW 3 -76 43 Left 0 SYMATTR Value Td=70n Z0=50 SYMATTR InstName T5 SYMBOL tline 432 32 R0 WINDOW 3 -76 43 Left 0 SYMATTR Value Td=50n Z0=75 SYMATTR InstName T6 SYMBOL res -64 192 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 50 SYMBOL res -64 -112 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R2 SYMATTR Value 50 TEXT 288 352 Left 0 !.tran 0 500n 0 1n TEXT -16 208 Bottom 0 ;IN+ TEXT -16 272 Bottom 0 ;IN- TEXT 528 208 Bottom 0 ;OUT- TEXT 536 288 Bottom 0 ;OUT+ TEXT -48 -96 Bottom 0 ;IN+ TEXT -48 -16 Bottom 0 ;IN- TEXT 560 -96 Bottom 0 ;OUT- TEXT 568 -16 Bottom 0 ;OUT+ TEXT 272 -104 Bottom 0 ;"Correct" TEXT 272 176 Bottom 0 ;"Incorrect"
I tried all sorts of things to change the outer-mode impedance (like putting dielectrics around the conductors) and nothing happens. A lossy dielectric (like a loaded pc board, or my fingers) inhibits the tiny ringing after the output step, but that's all.
The ferrite is just adding common-mode inductance, and it doesn't matter where it's placed, even around an SMA connector on the sampling head, so it's not affecting modes. Its permeability is probably close to 1 at the 40 ps risetime edge we're seeing.
This is a lot easier to build than it is to model, so why model?
John
John,
It could affect the current into the common mode, especially at LF. In the correct version of the simulation with four SPICE transmission line elements, it becomes an ideal inverting transmission line transformer pretty much no matter how the common mode current is driven to zero.
At the risk of being so fauxpaucious as to answer a rhetorical question, I would venture that a TDR would probably help understand the circuit at least as easily as SPICE transmission lines.
--Mike
Hello Mike,
It has outside field. To keep the Federales away (FCC) it might be good to shield somehow. On the lab bench I sometimes use Danish butter cookie cans for that but this leads to weight issues :-(
-- Regards, Joerg http://www.analogconsultants.com
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.