# Transmission line related question

• posted

Could some electronics guru please clarify the following. I have not used transmission line concepts for a while, and so would request a few clarifications. I have created a simple SPICE lossless transmission line with repeating LC stages and a cut-of frequency of 5KHz. Given that the reflection coefficient is rho = (Zt - Zo)/(Zt + Zo) where Zt is the termination impedance and Zo the characteristic impedance, my questions are:

1. If Zt is zero -- short, then rho = -1, and the reflected signal amplitude is -1 x input signal amplitude -- in the simulator however, the signal at the output node is very small, as the resistance to ground is practically zero, and the signal is shorted -- how do I observe the reflected signal ?
2. If Zt is infinite, then rho is +1, and once again how do I observe the reflected signal ? Currently, I can clearly see the phase difference between the input and output signals, but not the reflections, as I had hoped. The transmission line is connected in the traditional sense with a series resistance between its start node and the signal source and line start node, and termination resistance at the other end. Any hints, suggestions would be of immense help -- thanks in advance.
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• posted

At the input to the transmission line,after the source termination resistor - a step from the signal source will appear as a finite width pulse at the input to the transmission line and along the transmission line. At the input the pulsw width will be twice the length of the transmission line, dropping to zero as you move down the transmission line.

As a doubling of the step height all the way along the transmission line, right back to the input

What is you test signal? A Heavyside step or a square pulse are what show up in most discussions. Sine waves require more careful interpretation.

-- Bill Sloman, Nijmegen

• posted

What source impedance are you using to drive your transmission line? It also may not be "long" enough to see the reflection without setting a very small timestep in the simulator. ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |```
• posted

Any where along the line (delayed by the line length). You can also look at the current in the "short".

Measure it. The voltage at the far end will be twice what was sent (Vin + reflection).

• posted

The way to get Zt approaching zero is to make the capacitance per unit length approach infinite. It's hard to drive an infinite capacitor. There's no signal to see the reflection of.

Zt infinite meand it's really easy to drive. It has reflections, but the infinite impedance means that the reflections are too wimpy to show up against the generator impedance.

But how are you specifying an infinite impedance in a transmission line model? Or, for that matter, how are you constructing a transmission line with zero Zo?

Infinite circuit values stir up all sorts of silly dilemmas.

Did you make the transmission lines out of lumped L and C elements, or use the Spice lines and plug in the values? What L and C values did you use to get zero and infinite Z?

Using lumped Ls and Cs is a battle soon lost. The number of sections scales as Td/Tr squared.

John

• posted

I think that you are mistaking the total wave (which is what SPICE is showing you) for the reflected wave.

With the line short circuited, the voltage at the short circuit is equal to zero. In the simple case, you say "well duh, it's shorted". In the transmission line analysis case, you say that it is because the reflected wave is of equal amplitude and opposite sign, and V + -V = 0.

With the line open circuited, the voltage (assuming proper termination at the other end) is equal to twice what it would be if the line were properly terminated. In the "well duh" case this is because the line looking back to the source looks like an impedance of Zo and you've removed an equal and parallel impedance from the line. In the transmission line analysis case, you say that it is because the reflected wave is of equal amplitude and the same sign, and V + V = 2V.

Note that it now becomes simple to predict the reflected wave for _any_ terminating impedance (assuming proper source termination), without trying to memorize a formula: calculate the voltage that you'd see from a Thevinen source with impedance Vo and the given load (call it Vl), then subtract the voltage that you'd see with proper termination (call it V), then calculate the reflected voltage: Vr = Vl - V.

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• posted

• posted

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ttdesign.com

• posted

On Sun, 11 Dec 2011 20:53:14 -0800 (PST), Daku wrote:

Oops. I was misstating Zo as Zt. Too much holiday cheer.

But I don't understand the issue. You can build a transmission line from a string of Ls and Cs, and get Zo = sqrt(L/C)

If you drive that from a step generator with impedance Zo, you'll see a reflection at the line input if the far-end termination Zt is not Zo. It's tricky with lumped LCs because it takes a lot of sections to make a decent transmission line.

Here's a parameterized LC line I did a while back. It does show an inverted reflection for a shorted termination, but it's pretty ugly with just 12 sections.

You could do some cutting and pasting to make it have more sections, in which case it would look a little better.

John

Version 4 SHEET 1 4660 916 WIRE -80 128 -176 128 WIRE 80 128 0 128 WIRE 208 128 160 128 WIRE 352 128 288 128 WIRE 448 128 352 128 WIRE 576 128 528 128 WIRE 720 128 656 128 WIRE 816 128 720 128 WIRE 944 128 896 128 WIRE 1088 128 1024 128 WIRE 1184 128 1088 128 WIRE 1312 128 1264 128 WIRE 1456 128 1392 128 WIRE 1552 128 1456 128 WIRE 1680 128 1632 128 WIRE 1824 128 1760 128 WIRE 1920 128 1824 128 WIRE 2048 128 2000 128 WIRE 2192 128 2128 128 WIRE 2288 128 2192 128 WIRE 2416 128 2368 128 WIRE 2560 128 2496 128 WIRE 2656 128 2560 128 WIRE 2784 128 2736 128 WIRE 2928 128 2864 128 WIRE 3024 128 2928 128 WIRE 3152 128 3104 128 WIRE 3296 128 3232 128 WIRE 3392 128 3296 128 WIRE 3520 128 3472 128 WIRE 3664 128 3600 128 WIRE 3760 128 3664 128 WIRE 3888 128 3840 128 WIRE 4032 128 3968 128 WIRE 4128 128 4032 128 WIRE 4256 128 4208 128 WIRE 4400 128 4336 128 WIRE 4640 128 4400 128 WIRE 352 160 352 128 WIRE 720 160 720 128 WIRE 1088 160 1088 128 WIRE 1456 160 1456 128 WIRE 1824 160 1824 128 WIRE 2192 160 2192 128 WIRE 2560 160 2560 128 WIRE 2928 160 2928 128 WIRE 3296 160 3296 128 WIRE 3664 160 3664 128 WIRE 4032 160 4032 128 WIRE 4400 160 4400 128 WIRE -176 176 -176 128 WIRE 352 256 352 224 WIRE 720 256 720 224 WIRE 1088 256 1088 224 WIRE 1456 256 1456 224 WIRE 1824 256 1824 224 WIRE 2192 256 2192 224 WIRE 2560 256 2560 224 WIRE 2928 256 2928 224 WIRE 3296 256 3296 224 WIRE 3664 256 3664 224 WIRE 4032 256 4032 224 WIRE 4400 256 4400 224 WIRE 4640 288 4640 128 WIRE -176 304 -176 256 WIRE 4640 432 4640 368 FLAG 352 256 0 FLAG -176 304 0 FLAG 720 256 0 FLAG 4640 432 0 FLAG 1088 256 0 FLAG 1456 256 0 FLAG 1824 256 0 FLAG 2192 256 0 FLAG 2560 256 0 FLAG 2928 256 0 FLAG 3296 256 0 FLAG 3664 256 0 FLAG 4032 256 0 FLAG 4400 256 0 SYMBOL ind 64 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L1 SYMATTR Value {LX} SYMBOL res 304 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value {RX} SYMBOL cap 336 160 R0 SYMATTR InstName C1 SYMATTR Value {CX} SYMBOL voltage -176 160 R0 WINDOW 3 -314 -42 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(0 1 1u 2n 2n 1u) SYMATTR InstName V1 SYMBOL ind 432 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L2 SYMATTR Value {LX} SYMBOL res 672 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value {RX} SYMBOL cap 704 160 R0 SYMATTR InstName C2 SYMATTR Value {CX} SYMBOL res 16 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 50 SYMBOL res 4656 384 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R5 SYMATTR Value 1 SYMBOL ind 800 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L3 SYMATTR Value {LX} SYMBOL res 1040 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value {RX} SYMBOL cap 1072 160 R0 SYMATTR InstName C3 SYMATTR Value {CX} SYMBOL ind 1168 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L4 SYMATTR Value {LX} SYMBOL res 1408 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R6 SYMATTR Value {RX} SYMBOL cap 1440 160 R0 SYMATTR InstName C4 SYMATTR Value {CX} SYMBOL ind 1536 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L5 SYMATTR Value {LX} SYMBOL res 1776 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value {RX} SYMBOL cap 1808 160 R0 SYMATTR InstName C5 SYMATTR Value {CX} SYMBOL ind 1904 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L6 SYMATTR Value {LX} SYMBOL res 2144 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value {RX} SYMBOL cap 2176 160 R0 SYMATTR InstName C6 SYMATTR Value {CX} SYMBOL ind 2272 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L7 SYMATTR Value {LX} SYMBOL res 2512 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R9 SYMATTR Value {RX} SYMBOL cap 2544 160 R0 SYMATTR InstName C7 SYMATTR Value {CX} SYMBOL ind 2640 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L8 SYMATTR Value {LX} SYMBOL res 2880 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R10 SYMATTR Value {RX} SYMBOL cap 2912 160 R0 SYMATTR InstName C8 SYMATTR Value {CX} SYMBOL ind 3008 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L9 SYMATTR Value {LX} SYMBOL res 3248 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R11 SYMATTR Value {RX} SYMBOL cap 3280 160 R0 SYMATTR InstName C9 SYMATTR Value {CX} SYMBOL ind 3376 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L10 SYMATTR Value {LX} SYMBOL res 3616 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R12 SYMATTR Value {RX} SYMBOL cap 3648 160 R0 SYMATTR InstName C10 SYMATTR Value {CX} SYMBOL ind 3744 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L11 SYMATTR Value {LX} SYMBOL res 3984 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R13 SYMATTR Value {RX} SYMBOL cap 4016 160 R0 SYMATTR InstName C11 SYMATTR Value {CX} SYMBOL ind 4112 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L12 SYMATTR Value {LX} SYMBOL res 4352 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R14 SYMATTR Value {RX} SYMBOL cap 4384 160 R0 SYMATTR InstName C12 SYMATTR Value {CX} TEXT -424 176 Left 2 !.PARAM RX=0.01 TEXT -424 224 Left 2 !.PARAM CX=1n TEXT -432 272 Left 2 !.PARAM LX=2.5u TEXT -384 56 Left 2 !.tran 5u

• posted

Use a narrow pulse or a step.

• posted

On Dec 12, 12:33=A0am, John Larkin wrote: Thanks for the sample transmission line model below, but my own transmission line model is working fine right now. It consists of 300 LC sub-circuits, and each has L=3D5.625 H and C =3D 0.001 F to give a characteristic impedance of 75 Ohms. I have used simple resistive load resistors for the tests so far, and I see the reflections now.

• posted

Beg your pardon? Why would that be so?

If you want to get a feel for transmission line behaviour, don't bother with a chain of LC sections. You'd need an awful lot of sections for results to be clear-cut. Use a tline component.

To separate the incident signal from the reflection, use a bridge. Actual network analyzers do it much the same way.

Below an example in LTspice:

Jeroen Belleman

Version 4 SHEET 1 880 680 WIRE -448 128 -496 128 WIRE -176 128 -368 128 WIRE -144 128 -176 128 WIRE -16 128 -64 128 WIRE 128 128 -16 128 WIRE 304 128 224 128 WIRE 400 128 384 128 WIRE -176 208 -176 128 WIRE -16 288 -16 128 WIRE 96 288 -16 288 WIRE 256 288 176 288 WIRE 320 288 256 288 WIRE 416 288 400 288 WIRE -176 368 -176 288 WIRE -16 368 -176 368 WIRE 96 368 -16 368 WIRE 240 368 176 368 WIRE -176 384 -176 368 WIRE -176 480 -176 464 FLAG 128 160 0 FLAG 224 160 0 FLAG -496 128 0 FLAG 400 128 0 FLAG -176 480 0 FLAG 240 368 0 FLAG 256 288 reflection FLAG 416 288 0 FLAG -16 368 incident SYMBOL tline 176 144 R0 SYMATTR InstName T1 SYMBOL res -48 112 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 50 SYMBOL res 288 144 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R2 SYMATTR Value 1m SYMBOL res -192 192 R0 SYMATTR InstName R3 SYMATTR Value 50 SYMBOL res -192 368 R0 SYMATTR InstName R4 SYMATTR Value 50 SYMBOL bv -352 128 R90 WINDOW 0 -32 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName B1 SYMATTR Value V=2*exp(-0.5*pwr(time/10n-3,2)) SYMBOL ind2 80 304 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L1 SYMATTR Value 1 SYMATTR Type ind SYMBOL ind2 80 384 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L2 SYMATTR Value 1 SYMATTR Type ind SYMBOL res 304 304 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R5 SYMATTR Value 1g TEXT 120 56 Left 0 !.tran 200n TEXT 72 432 Left 0 !K12 L1 L2 1

• posted

Dear Sir, I am afraid I use HSpice and ngspice both of which use a text file input -- unlike the LTSpice circuit description below. Could you please explain the bridge that you mention below, so that I can then add it to my model. Also, I have a total of 500 LC cells in my design right now, so I think it should provide some meaningful results.

• posted

It's just a Wheatstone bridge with one of the sides replaced by the transmission line. Signal is applied between top and bottom, and the reflection appears across. I used a balun to transform it to a ground-referenced signal. This is exactly what the HP3577A-HP35677A VNA does, for example.

Here is the netlist of the same thing. You may have to tweak a few things to get your flavour of Spice to swallow it.

Regards, Jeroen Belleman

------------------------ T1 N002 0 N003 0 Td=50n Z0=50 R1 N002 N001 50 R2 N003 0 1m R3 N001 incident 50 R4 incident 0 50 B1 N001 0 V=2*exp(-0.5*pwr(time/50n-3,2)) L1 N002 reflection 1 L2 incident 0 1 R5 reflection 0 1g .tran 1u K12 L1 L2 1 .end

• posted

To check if you have enough 'cells'

Of course DC is pretty accurate. At higher frequency the 'lumped' model becomes inaccurate. Depending upon what you're trying to do that upper cutoff frequency can either be around 1/3 the resonance of the lumped cell, or as low as 1/10. That translates to the cell's components being small in value resonating at least 3X, to 10X, the frequency of interest. And *IF* you put a step into your transmission model that has frequency content ABOVE that cutoff frequency, you have violated the model and should not trust the results too much.

Adding even more to this don't forget about skin effect shifting your series R substantially.

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