Inbuilt Wifi

Jan 21, 2021 12 Replies

For reasons not pertinent to PIs, I started researching wifi performance, and would like the assembled multitudes to comment on the correctness, or otherwise of what I have found.


- All Pis with built-in Wifi use the Broadcomm chip



- This chip is not capable of 5Ghz connectivity



- Nor is it capable of 40Mhz dual channel operation



- ergo it *cannot* connect at *more* than 72Mbps



And its often _way_ worse than that.



?The fundamental cause of the trouble in the modern world today is that the stupid are cocksure while the intelligent are full of doubt." - Bertrand Russell

Both my Pi3B+ connect to my 5Ghz wifi.

Chris Elvidge England

+++!

can you show what chipsets/drivers and what protocols they are using?

It would be nice to tabulate the results

?A leader is best When people barely know he exists. Of a good leader, who talks little,When his work is done, his aim fulfilled,They will say, ?We did this ourselves.? ? Lao Tzu, Tao Te Ching

The Pi 3B+ and 4B have 5 GHz WiFi. I think the chips support 40MHz on

2.4GHz, but the driver doesn't.

All my 3B+s and 4Bs have Ethernet, so I can't check on the 5GHz performance, but the 3Bs and Zeros scattered around the house do about

20-30Mbps up and down, as do the 2Bs with USB WiFi adaptors.

Just failed over a 4B on to 5GHz WiFi, its fairly close to the router but only gives 88.6Mbs down, and 75.3 Mbs up.

So I recommend if you need speed, use Ethernet. Up to the 3B you should get 96/92Mbps, the 3B+ does 327/270Mbs, and the 937/832MBps down/up.

---druck

lshw shows:

*-network description: Wireless interface physical id: 2 logical name: wlan0 serial: b8:27:eb:fb:cc:a1 capabilities: ethernet physical wireless configuration: broadcast=yes driver=brcmfmac driverversion=7.45.206 firmware=01-88ee44ea ip=192.168.23.152 multicast=yes wireless=IEEE 802.11

iwconfig: wlan0 IEEE 802.11 ESSID:"CHRISPLACE-A" Mode:Managed Frequency:5.3 GHz Access Point: 80:3F:5D:FA:4D:FA Bit Rate=78 Mb/s Tx-Power=31 dBm Retry short limit:7 RTS thr:off Fragment thr:off Encryption key:off Power Management:on Link Quality=70/70 Signal level=-31 dBm Rx invalid nwid:0 Rx invalid crypt:0 Rx invalid frag:0 Tx excessive retries:0 Invalid misc:0 Missed beacon:0

# cat /sys/class/net/wlan0/device/vendor

0x02d0 # cat /sys/class/net/wlan0/device/device 0xa9a6

02d0 is Broadcom

Chris Elvidge England

The 3B+ and 4 have 5 GHz capable wifi, apparently using the Cypress CYW43455 says

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although when you follow the link to Cypress it says the chip can only do Bluetooth 4.1 but RPi says it supports 5.0. So, something not right. Would be strange to have a non-broadcom wifi chip on broadcom's baby.

3b+ 4b & pi400 all speak 5ghz

not sure about max speed

> I thing you're missing the capability of Makefiles. It takes several _hours_ to do `make' a second time on my machine with the latest glibc sources (and no files are recompiled a second time). I think I'll remove `build' after changing one file if I want to recompile it. -- Juan Cespedes

It is indeed a Cyprus chip and yes it does support BT 5.0 as per datasheet linked here..

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Cypress bought the Wi-Fi assets from Broadcom, hence it's now a Cypress part that was designed by Broadcom, using Broadcom's vendor ID.

Theo

Op 21-01-2021 om 16:24 schreef The Natural Philosopher:

See also

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with pertinent quote: "for CYW43455 WiFi chip. It should finally make

80MHz channels a reality and hopefully solve a number of connectivity problems" Related discussion linked from there.

Op 25-01-2021 om 09:12 schreef A. Dumas:

Oh wow, from one of the first posts there: "So link bumped to 433 from

200 [Mb/s]". That looks promising.
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Op 25-01-2021 om 09:16 schreef A. Dumas:

D'oh! From a bit further: "The WiFi chip is connected via a 4-bit SDIO link that typically runs at 41.7MHz giving an upper limit on throughput of ~160Mbs."

So the link going to 433 Mb/s won't make a difference, except in this sense: "being able to properly use the wide channels means that the channel (which is a shared medium) is occupied for a shorter time, leaving more time for other devices."

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Op 25-01-2021 om 09:27 schreef A. Dumas:

Tiny bit more detail in a different thread for the xxx56 version (which is in the Pi400):

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"In terms of improving your throughput further you are probably limited by the SDIO interface. "sudo cat /sys/kernel/debug/mmc1/ios" shows the state of that link. The bus clock has to be an even integer divisor of the emmc clock, which is currently fixed at 250MHz, hence the 41.67MHz. Tweaking the EMMC clock ought to make 50MHz attainable, but for clock synchronisation reasons that would also require changing the core clock. Although not trivial, I think there are potential gains to be made here."

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