Texas Instruments MSP430 datasheet

MIXED SIGNAL MICROCONTROLLER

FEATURES

• Low Supply-Voltage Range: 1.8 V to 3.6 V
• Ultra-Low Power Consumption
  • Active Mode: 230 μA at 1 MHz, 2.2 V
  • Standby Mode: 0.5 μA
  • Off Mode (RAM Retention): 0.1 μA
• Five Power-Saving Modes
• Ultra-Fast Wake-Up From Standby Mode in Less Than 1 μs
• 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time
• Basic Clock Module Configurations
  • Internal Frequencies up to 16 MHz With Four Calibrated Frequency
  • Internal Very-Low-Power Low-Frequency (LF) Oscillator
  • 32-kHz Crystal
  • External Digital Clock Source
• Two 16-Bit Timer_A With Three Capture/Compare Registers
• Up to 24 Capacitive-Touch Enabled I/O Pins
• Universal Serial Communication Interface (USCI)
  • Enhanced UART Supporting Auto Baudrate Detection (LIN)
  • IrDA Encoder and Decoder
  • Synchronous SPI
  • I²C™
• On-Chip Comparator for Analog Signal Compare Function or Slope Analog-to-Digital (A/D) Conversion
• 10-Bit 200-ksps Analog-to-Digital (A/D) Converter With Internal Reference, Sample-and-Hold, and Autoscan (See Table 1)
• Brownout Detector
• Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse
• On-Chip Emulation Logic With Spy-Bi-Wire Interface
• Family Members are Summarized in Table 1
• Package Options
  • TSSOP: 20 Pin, 28 Pin
  • PDIP: 20 Pin
  • QFN: 32 Pin
• For Complete Module Descriptions, See the MSP430x2xx Family User’s Guide (SLAU144)

DESCRIPTION

The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 μs.

The MSP430G2x13 and MSP430G2x53 series are ultra-low-power mixed signal microcontrollers with built-in 16-bit timers, up to 24 I/O capacitive-touch enabled pins, a versatile analog comparator, and built-in communication capability using the universal serial communication interface. In addition the MSP430G2x53 family members have a 10-bit analog-to-digital (A/D) converter. For configuration details see Table 1.

Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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Table 1. Available Options (1)(2)

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

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MSP430G2x53

MSP430G2x13

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Device Pinout, MSP430G2x13 and MSP430G2x53, 20-Pin Devices, TSSOP and PDIP

NOTE: ADC10 is available on MSP430G2x53 devices only. NOTE: The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.

Device Pinout, MSP430G2x13 and MSP430G2x53, 28-Pin Devices, TSSOP

NOTE: ADC10 is available on MSP430G2x53 devices only.

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Device Pinout, MSP430G2x13 and MSP430G2x53, 32-Pin Devices, QFN

NOTE: ADC10 is available on MSP430G2x53 devices only.

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Functional Block Diagram, MSP430G2x53

NOTE: Port P3 is available on 28-pin and 32-pin devices only.

Functional Block Diagram, MSP430G2x13

NOTE: Port P3 is available on 28-pin and 32-pin devices only.

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Table 2. Terminal Functions

(1) MSP430G2x53 devices only

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Table 2. Terminal Functions (continued)

(2) TDO or TDI is selected via JTAG instruction.

(3) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset.

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Table 2. Terminal Functions (continued)

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SHORT-FORM DESCRIPTION

CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.

Instruction Set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 3 shows examples of the three types of instruction formats; Table 4 shows the address modes.

Table 3. Instruction Word Formats

Table 4. Address Mode Descriptions (1)

(1) S = source, D = destination

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Operating Modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

• Active mode (AM)
  • All clocks are active
• Low-power mode 0 (LPM0)
  • CPU is disabled
  • ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 1 (LPM1)
  • CPU is disabled
  • ACLK and SMCLK remain active, MCLK is disabled
  • DCO's dc generator is disabled if DCO not used in active mode
• Low-power mode 2 (LPM2)
  • CPU is disabled
  • MCLK and SMCLK are disabled
  • DCO's dc generator remains enabled
  • ACLK remains active
• Low-power mode 3 (LPM3)
  • CPU is disabled
  • MCLK and SMCLK are disabled
  • DCO's dc generator is disabled
  • ACLK remains active
• Low-power mode 4 (LPM4)
  • CPU is disabled
  • ACLK is disabled
  • MCLK and SMCLK are disabled
  • DCO's dc generator is disabled
  • Crystal oscillator is stopped

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Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the CPU goes into LPM4 immediately after power-up.

Table 5. Interrupt Sources, Flags, and Vectors

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address ranges.

(2) Multiple source flags

(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

(4) Interrupt flags are located in the module.

(5) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.

(6) In UART or SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.

(7) This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h) disables the erasure of the flash if an invalid password is supplied.

(8) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if necessary.

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Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

Legend

• rw: Bit can be read and written.
• rw-0,1: Bit can be read and written. It is reset or set by PUC.
• rw-(0,1): Bit can be read and written. It is reset or set by POR.
• □□□ SFR bit is not present in device.

Table 6. Interrupt Enable Register 1 and 2

• WDTIE: Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode.
• OFIE: Oscillator fault interrupt enable
• NMIIE: (Non)maskable interrupt enable
• ACCVIE: Flash access violation interrupt enable

• UCA0RXIE: USCI_A0 receive interrupt enable
• UCA0TXIE: USCI_A0 transmit interrupt enable
• UCB0RXIE: USCI_B0 receive interrupt enable
• UCB0TXIE: USCI_B0 transmit interrupt enable

Table 7. Interrupt Flag Register 1 and 2

• WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
• OFIFG: Flag set on oscillator fault.
• PORIFG: Power-On Reset interrupt flag. Set on VCC power-up.
• RSTIFG: External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
• NMIIFG: Set via RST/NMI pin

• UCA0RXIFG: USCI_A0 receive interrupt flag
• UCA0TXIFG: USCI_A0 transmit interrupt flag
• UCB0RXIFG: USCI_B0 receive interrupt flag
• UCB0TXIFG: USCI_B0 transmit interrupt flag

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Memory Organization

Table 8. Memory Organization

Bootstrap Loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319).

Table 9. BSL Function Pins

Flash Memory

The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required.

MSP430G2x53

TEXAS INSTRUMENTS

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Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 \mus. The basic clock module provides the following clock signals:

• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.

Main DCO Characteristics

• All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15.
• DCO control bits DCOx have a step size as defined by parameter S$_{DCO}$.
• Modulation control bits MODx select how often f${DCO(RSEL,DCO+1)}$ is used within the period of 32 DCOCLK cycles. The frequency f${DCO(RSEL,DCO)}$ is used for the remaining cycles. The frequency is an average equal to:

$f_average = \frac32 × f_DCO(RSEL,DCO) × f_DCO(RSEL,DCO+1)MOD × f_DCO(RSEL,DCO) + (32 - MOD) × f_DCO(RSEL,DCO+1)$

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Calibration Data Stored in Information Memory Segment A

Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure.

Table 10. Tags Used by the ADC Calibration Tags

Table 11. Labels Used by the ADC Calibration Tags

Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.

Digital I/O

Up to three 8-bit I/O ports are implemented:

• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible.
• Edge-selectable interrupt input capability for all bits of port P1 and port P2 (if available).
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup or pulldown resistor.
• Each I/O has an individually programmable pin oscillator enable bit to enable low-cost capacitive touch detection.

Watchdog Timer (WDT+)

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.

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Timer_A3 (TA0, TA1)

Timer0/1_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 12. Timer0_A3 Signal Connections

Table 13. Timer1_A3 Signal Connections

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MSP430G2x53

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Universal Serial Communications Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. Not all packages support the USCI functionality.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.

USCI_B0 provides support for SPI (3 or 4 pin) and I2C.

Comparator_A+

The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.

ADC10 (MSP430G2x53 Only)

The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion result handling, allowing ADC samples to be converted and stored without any CPU intervention.

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Peripheral File Map

Table 14. Peripherals With Word Access

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Table 15. Peripherals With Byte Access

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Table 15. Peripherals With Byte Access (continued)

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Absolute Maximum Ratings (1)

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

Recommended Operating Conditions

Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)

(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the specified maximum frequency.

(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.

Figure 1. Safe Operating Area

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Electrical Characteristics

Active Mode Supply Current Into VCC Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)(2)

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.

Typical Characteristics, Active Mode Supply Current (Into VCC)

Figure 2. Active Mode Current vs VCC, TA = 25°C

Figure 3. Active Mode Current vs DCO Frequency

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Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.

(3) Current for brownout and WDT clocked by SMCLK included.

(4) Current for brownout and WDT clocked by ACLK included.

(5) Current for brownout included.

Typical Characteristics, Low-Power Mode Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Figure 4. LPM3 Current vs Temperature

Figure 5. LPM4 Current vs Temperature

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Schmitt-Trigger Inputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Leakage Current, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.

Outputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.

Output Frequency, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1) A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider.

(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

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Typical Characteristics, Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE

V$_{OL}$ – Low-Level Output Voltage – V Figure 6.

TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE

V$_{OL}$ – Low-Level Output Voltage – V Figure 7.

TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE

V$_{OH}$ – High-Level Output Voltage – V Figure 8.

TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE

V$_{OH}$ – High-Level Output Voltage – V Figure 9.

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