Microchip ENC28J60 datasheet: 4.0 Serial peripheral interface (SPI)

4.0 SERIAL PERIPHERAL INTERFACE (SPI)

4.1 Overview

The ENC28J60 is designed to interface directly with the Serial Peripheral Interface (SPI) port available on many microcontrollers. The implementation used on this device supports SPI mode 0,0 only. In addition, the SPI port requires that SCK be at Idle in a low state; selectable clock polarity is not supported.

Commands and data are sent to the device via the SI pin, with data being clocked in on the rising edge of SCK. Data is driven out by the ENC28J60 on the SO line, on the falling edge of SCK. The CS pin must be held low while any operation is performed and returned high when finished.

FIGURE 4-1: SPI INPUT TIMING

FIGURE 4-2: SPI OUTPUT TIMING

4.2 SPI Instruction Set

The operation of the ENC28J60 depends entirely on commands given by an external host controller over the SPI interface. These commands take the form of instructions, of one or more bytes, which are used to access the control memory and Ethernet buffer spaces. At the least, instructions consist of a 3-bit opcode, followed by a 5-bit argument that specifies either a register address or a data constant. Write and bit field instructions are also followed by one or more bytes of data.

A total of seven instructions are implemented on the ENC28J60. Table 4-1 shows the command codes for all operations.

TABLE 4-1: SPI INSTRUCTION SET FOR THE ENC28J60

Legend: a = Control Register Address, d = Data Payload

4.2.1 READ CONTROL REGISTER COMMAND

The Read Control Register (RCR) command allows the host controller to read any of the ETH, MAC and MII registers in any order. The contents of the PHY registers are read via a special MII register interface (see Section 3.3.1 “Reading PHY Registers” for more information).

The RCR command is started by pulling the \overlineCS pin low. The RCR opcode is then sent to the ENC28J60, followed by a 5-bit register address (A4 through A0). The 5-bit address identifies any of the 32 control registers in the current bank. If the 5-bit address is an ETH register, then data in the selected register will immediately start shifting out MSb first on the SO pin. Figure 4-3 shows the read sequence for these registers.

If the address specifies one of the MAC or MII registers, a dummy byte will first be shifted out on the SO pin. After the dummy byte, the data will be shifted out MSb first on the SO pin. The RCR operation is terminated by raising the \overlineCS pin. Figure 4-4 shows the read sequence for MAC and MII registers.

FIGURE 4-3: READ CONTROL REGISTER COMMAND SEQUENCE (ETH REGISTERS)

FIGURE 4-4: READ CONTROL REGISTER COMMAND SEQUENCE (MAC AND MII REGISTERS)

4.2.2 READ BUFFER MEMORY COMMAND

The Read Buffer Memory (RBM) command allows the host controller to read bytes from the integrated 8-Kbyte transmit and receive buffer memory.

If the AUTOINC bit in the ECON2 register is set, the ERDPT Pointer will automatically increment to point to the next address after the last bit of each byte is read. The next address will normally be the current address incremented by one. However, if the last byte in the receive buffer is read (ERDPT = ERXND), the ERDPT Pointer will change to the beginning of the receive buffer (ERXST). This allows the host controller to read packets from the receive buffer in a continuous stream without keeping track of when a wraparound is needed. If AUTOINC is set when address, 1FFFh, is read and ERXND does not point to this address, the Read Pointer will increment and wrap around to 0000h.

The RBM command is started by pulling the \overlineCS pin low. The RBM opcode is then sent to the ENC28J60, followed by the 5-bit constant, 1Ah. After the RBM command and constant are sent, the data stored in the memory pointed to by ERDPT will be shifted out MSb first on the SO pin. If the host controller continues to provide clocks on the SCK pin, without raising \overlineCS, the byte pointed to by ERDPT will again be shifted out MSb first on the SO pin. In this manner, with AUTOINC enabled, it is possible to continuously read sequential bytes from the buffer memory without any extra SPI command overhead. The RBM command is terminated by raising the \overlineCS pin.

4.2.3 WRITE CONTROL REGISTER COMMAND

The Write Control Register (WCR) command allows the host controller to write to any of the ETH, MAC and MII Control registers in any order. The PHY registers are written to via a special MII register interface (see Section 3.3.2 “Writing PHY Registers” for more information).

The WCR command is started by pulling the \overlineCS pin low. The WCR opcode is then sent to the ENC28J60, followed by a 5-bit address (A4 through A0). The 5-bit address identifies any of the 32 control registers in the current bank. After the WCR command and address are sent, actual data that is to be written is sent, MSb first. The data will be written to the addressed register on the rising edge of the SCK line.

The WCR operation is terminated by raising the \overlineCS pin. If the \overlineCS line is allowed to go high before eight bits are loaded, the write will be aborted for that data byte. Refer to the timing diagram in Figure 4-5 for a more detailed illustration of the byte write sequence.

FIGURE 4-5: WRITE CONTROL REGISTER COMMAND SEQUENCE

4.2.4 WRITE BUFFER MEMORY COMMAND

The Write Buffer Memory (WBM) command allows the host controller to write bytes to the integrated 8-Kbyte transmit and receive buffer memory.

If the AUTOINC bit in the ECON2 register is set, after the last bit of each byte is written, the EWRPT Pointer will automatically be incremented to point to the next sequential address (Current Address + 1). If address, 1FFFh, is written with AUTOINC set, the Write Pointer will increment to 0000h.

The WBM command is started by lowering the \overlineCS pin. The WBM opcode should then be sent to the ENC28J60, followed by the 5-bit constant, 1Ah. After the WBM command and constant are sent, the data to be stored in the memory pointed to by EWRPT should be shifted out MSb first to the ENC28J60. After 8 data bits are received, the Write Pointer will automatically increment if AUTOINC is set. The host controller can continue to provide clocks on the SCK pin and send data on the SI pin, without raising \overlineCS, to keep writing to the memory. In this manner, with AUTOINC enabled, it is possible to continuously write sequential bytes to the buffer memory without any extra SPI command overhead.

The WBM command is terminated by bringing up the \overlineCS pin. Refer to Figure 4-6 for a detailed illustration of the write sequence.

4.2.5 BIT FIELD SET COMMAND

The Bit Field Set (BFS) command is used to set up to 8 bits in any of the ETH Control registers. Note that this command cannot be used on the MAC registers, MII registers, PHY registers or buffer memory. The BFS command uses the provided data byte to perform a bit-wise OR operation on the addressed register contents.

The BFS command is started by pulling the \overlineCS pin low. The BFS opcode is then sent, followed by a 5-bit address (A4 through A0). The 5-bit address identifies any of the ETH registers in the current bank. After the BFS command and address are sent, the data byte containing the bit field set information should be sent, MSb first. The supplied data will be logically ORed to the content of the addressed register on the rising edge of the SCK line for the D0 bit.

If the \overlineCS line is brought high before eight bits are loaded, the operation will be aborted for that data byte. The BFS operation is terminated by raising the \overlineCS pin.

4.2.6 BIT FIELD CLEAR COMMAND

The Bit Field Clear (BFC) command is used to clear up to 8 bits in any of the ETH Control registers. Note that this command cannot be used on the MAC registers, MII registers, PHY registers or buffer memory. The BFC command uses the provided data byte to perform a bit-wise NOTAND operation on the addressed register contents. As an example, if a register had the contents of F1h and the BFC command was executed with an operand of 17h, then the register would be changed to have the contents of E0h.

The BFC command is started by lowering the \overlineCS pin. The BFC opcode should then be sent, followed by a 5-bit address (A4 through A0). The 5-bit address identifies any of the ETH registers in the current bank. After the BFC command and address are sent, a data byte containing the bit field clear information should be sent, MSb first. The supplied data will be logically inverted and subsequently ANDed to the contents of the addressed register on the rising edge of the SCK line for the D0 bit.

The BFC operation is terminated by bringing the \overlineCS pin high. If \overlineCS is brought high before eight bits are loaded, the operation will be aborted for that data byte.

FIGURE 4-6: WRITE BUFFER MEMORY COMMAND SEQUENCE

4.2.7 SYSTEM RESET COMMAND

The System Reset Command (SRC) allows the host controller to issue a System Soft Reset command. Unlike other SPI commands, the SRC is only a single byte command and does not operate on any register.

The command is started by pulling the \overlineCS pin low. The SRC opcode is the sent, followed by a 5-bit Soft Reset command constant of 1Fh. The SRC operation is terminated by raising the CS pin.

Figure 4-7 shows a detailed illustration of the System Reset Command sequence. For more information on SRC’s Soft Reset, refer to Section 11.2 “System Reset”.

FIGURE 4-7: SYSTEM RESET COMMAND SEQUENCE

5.0 ETHERNET OVERVIEW

Before discussing the use of the ENC28J60 as an Ethernet interface, it may be helpful to review the structure of a typical data frame. Users requiring more information should refer to the IEEE 802.3 standard which is the basis for the Ethernet protocol.

5.1 Packet Format

Normal IEEE 802.3 compliant Ethernet frames are between 64 and 1518 bytes long. They are made up of five or six different fields: a destination MAC address, a source MAC address, a type/length field, data payload, an optional padding field and a Cyclic Redundancy Check (CRC). Additionally, when transmitted on the Ethernet medium, a 7-byte preamble field and Start-of-Frame (SOF) delimiter byte are appended to the beginning of the Ethernet packet. Thus, traffic seen on the twisted-pair cabling will appear as shown in Figure 5-1.

5.1.1 PREAMBLE/START-OF-FRAME DELIMITER

When transmitting and receiving data with the ENC28J60, the preamble and Start-of-Frame delimiter bytes will automatically be generated or stripped from the packets when they are transmitted or received. The host controller does not need to concern itself with them. Normally, the host controller will also not need to concern itself with padding and the CRC which the ENC28J60 will also be able to automatically generate when transmitting and verify when receiving. The padding and CRC fields will, however, be written into the receive buffer when packets arrive, so they may be evaluated by the host controller if needed.

FIGURE 5-1: ETHERNET PACKET FORMAT

Note 1: The FCS is transmitted starting with bit 31 and ending with bit 0.

5.1.2 DESTINATION ADDRESS

The destination address field is a 6-byte field filled with the MAC address of the device that the packet is directed to. If the Least Significant bit in the first byte of the MAC address is set, the address is a Multicast destination. For example, 01-00-00-00-F0-00 and 33-45-67-89-AB-CD are Multicast addresses, while 00-00-00-00-F0-00 and 32-45-67-89-AB-CD are not.

Packets with Multicast destination addresses are designed to arrive and be important to a selected group of Ethernet nodes. If the destination address field is the reserved Multicast address, FF-FF-FF-FF-FF-FF, the packet is a Broadcast packet and it will be directed to everyone sharing the network. If the Least Significant bit in the first byte of the MAC address is clear, the address is a Unicast address and will be designed for usage by only the addressed node.

The ENC28J60 incorporates receive filters which can be used to discard or accept packets with Multicast, Broadcast and/or Unicast destination addresses. When transmitting packets, the host controller is responsible for writing the desired destination address into the transmit buffer.

5.1.3 SOURCE ADDRESS

The source address field is a 6-byte field filled with the MAC address of the node which created the Ethernet packet. Users of the ENC28J60 must generate a unique MAC address for each controller used.

MAC addresses consist of two portions. The first three bytes are known as the Organizationally Unique Identifier (OUI). OUIs are distributed by the IEEE. The last three bytes are address bytes at the discretion of the company that purchased the OUI.

When transmitting packets, the assigned source MAC address must be written into the transmit buffer by the host controller. The ENC28J60 will not automatically transmit the contents of the MAADR registers which are used for the Unicast receive filter.

5.1.4 TYPE/LENGTH

The type/length field is a 2-byte field which defines which protocol the following packet data belongs to. Alternately, if the field is filled with the contents of 05DCh (1500) or any smaller number, the field is considered a length field and it specifies the amount of non-padding data which follows in the data field. Users implementing proprietary networks may choose to treat this field as a length field, while applications implementing protocols such as the Internet Protocol (IP) or Address Resolution Protocol (ARP), should program this field with the appropriate type defined by the protocol’s specification when transmitting packets.

5.1.5 DATA

The data field is a variable length field, anywhere from 0 to 1500 bytes. Larger data packets will violate Ethernet standards and will be dropped by most Ethernet nodes. The ENC28J60, however, is capable of transmitting and receiving larger packets when the Huge Frame Enable bit is set (MACON3.HFRMEN = 1).

5.1.6 PADDING

The padding field is a variable length field added to meet IEEE 802.3 specification requirements when small data payloads are used. The destination, source, type, data and padding of an Ethernet packet must be no smaller than 60 bytes. Adding the required 4-byte CRC field, packets must be no smaller than 64 bytes. If the data field is less than 46 bytes long, a padding field is required.

When transmitting packets, the ENC28J60 automatically generates zero-padding if the MACON3.PADCFG<2:0> bits are configured to do so. Otherwise, the host controller should manually add padding to the packet before transmitting it. The ENC28J60 will not prevent the transmission of undersize packets should the host controller command such an action.

When receiving packets, the ENC28J60 automatically rejects packets which are less than 18 bytes; it is assumed that a packet this small does not contain even the minimum of source and destination addresses, type information and FCS checksum required for all packets. All packets 18 bytes and larger will be subject to the standard receive filtering criteria and may be accepted as normal traffic. To conform with IEEE 802.3 requirements, the application itself will need to inspect all received packets and reject those smaller than 64 bytes.

5.1.7 CRC

The CRC field is a 4-byte field which contains an industry standard 32-bit CRC calculated with the data from the destination, source, type, data and padding fields.

When receiving packets, the ENC28J60 will check the CRC of each incoming packet. If ERXFCON.CRCEN is set, packets with invalid CRCs will automatically be discarded. If CRCEN is clear and the packet meets all other receive filtering criteria, the packet will be written into the receive buffer and the host controller will be able to determine if the CRC was valid by reading the receive status vector (see Section 7.2 “Receiving Packets”).

When transmitting packets, the ENC28J60 will automatically generate a valid CRC and transmit it if the MACON3.PADCFG<2:0> bits are configured to cause this. Otherwise, the host controller must generate the CRC and place it in the transmit buffer. Given the complexity of calculating a CRC, it is highly recommended that the PADCFG bits be configured such that the ENC28J60 will automatically generate the CRC field.

6.0 INITIALIZATION

Before the ENC28J60 can be used to transmit and receive packets, certain device settings must be initialized. Depending on the application, some configuration options may need to be changed. Normally, these tasks may be accomplished once after Reset and do not need to be changed thereafter.

6.1 Receive Buffer

Before receiving any packets, the receive buffer must be initialized by programming the ERXST and ERXND Pointers. All memory between and including the ERXST and ERXND addresses will be dedicated to the receive hardware. It is recommended that the ERXST Pointer be programmed with an even address.

Applications expecting large amounts of data and frequent packet delivery may wish to allocate most of the memory as the receive buffer. Applications that may need to save older packets or have several packets ready for transmission should allocate less memory.

When programming the ERXST or ERXND Pointer, the internal hardware copy of the ERXWRPT registers will automatically be updated with the value of ERXST. This value will be used as the starting location when the receive hardware begins writing received data. The ERXWRPT registers are updated by the hardware only when a new packet is successfully received.

Note: After writing to ERXST or ERXND, the ERXWRPT registers are not updated immediately; only the internal hardware copy of the ERXWRPT registers is updated. Therefore, comparing if (ERXWRPT = = ERXST) is not practical in a firmware initialization routine.

For tracking purposes, the ERXRDPT registers should additionally be programmed with the same value. To program ERXRDPT, the host controller must write to ERXRDPTL first, followed by ERXRDPTH. See Section 7.2.4 "Freeing Receive Buffer Space" for more information.

6.2 Transmit Buffer

All memory which is not used by the receive buffer is considered the transmission buffer. Data which is to be transmitted should be written into any unused space. After a packet is transmitted, however, the hardware will write a seven-byte status vector into memory after the last byte in the packet. Therefore, the host controller should leave at least seven bytes between each packet and the beginning of the receive buffer. No explicit action is required to initialize the transmission buffer.

6.3 Receive Filters

The appropriate receive filters should be enabled or disabled by writing to the ERXFCON register. See Section 8.0 "Receive Filters" for information on how to configure it.

6.4 Waiting for OST

If the initialization procedure is being executed immediately following a Power-on Reset, the ESTAT.CLKRDY bit should be polled to make certain that enough time has elapsed before proceeding to modify the MAC and PHY registers. For more information on the OST, see Section 2.2 "Oscillator Start-up Timer".

6.5 MAC Initialization Settings

Several of the MAC registers require configuration during initialization. This only needs to be done once; the order of programming is unimportant.

1. Set the MARXEN bit in MACON1 to enable the MAC to receive frames. If using full duplex, most applications should also set TXPAUS and RXPAUS to allow IEEE defined flow control to function.
2. Configure the PADCFG, TXCRCEN and FULDPX bits of MACON3. Most applications should enable automatic padding to at least 60 bytes and always append a valid CRC. For convenience, many applications may wish to set the FRMLNEN bit as well to enable frame length status reporting. The FULDPX bit should be set if the application will be connected to a full-duplex configured remote node; otherwise, it should be left clear.
3. Configure the bits in MACON4. For conformance to the IEEE 802.3 standard, set the DEFER bit.
4. Program the MAMXFL registers with the maximum frame length to be permitted to be received or transmitted. Normal network nodes are designed to handle packets that are 1518 bytes or less.
5. Configure the Back-to-Back Inter-Packet Gap register, MABBIPG. Most applications will program this register with 15h when Full-Duplex mode is used and 12h when Half-Duplex mode is used.
6. Configure the Non-Back-to-Back Inter-Packet Gap register low byte, MAIPGL. Most applications will program this register with 12h.
7. If half duplex is used, the Non-Back-to-Back Inter-Packet Gap register high byte, MAIPGH, should be programmed. Most applications will program this register to 0Ch.
8. If Half-Duplex mode is used, program the Retransmission and Collision Window registers, MACLCON1 and MACLCON2. Most applications will not need to change the default Reset values. If the network is spread over exceptionally long cables, the default value of MACLCON2 may need to be increased.
9. Program the local MAC address into the MAADR1:MAADR6 registers.

REGISTER 6-1: MACON1: MAC CONTROL REGISTER 1

Legend: R = Readable bit -n = Value at POR r = Reserved bit W = Writable bit '1' = Bit is set U = Unimplemented bit, read as '0' '0' = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’ bit 4 Reserved: Maintain as ‘0’ bit 3 TXPAUS: Pause Control Frame Transmission Enable bit 1 = Allow the MAC to transmit pause control frames (needed for flow control in full duplex) 0 = Disallow pause frame transmissions bit 2 RXPAUS: Pause Control Frame Reception Enable bit 1 = Inhibit transmissions when pause control frames are received (normal operation) 0 = Ignore pause control frames which are received bit 1 PASSALL: Pass All Received Frames Enable bit 1 = Control frames received by the MAC will be written into the receive buffer if not filtered out 0 = Control frames will be discarded after being processed by the MAC (normal operation) bit 0 MARXEN: MAC Receive Enable bit 1 = Enable packets to be received by the MAC 0 = Disable packet reception

REGISTER 6-2: MACON3: MAC CONTROL REGISTER 3

Legend:

R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 7-5 PADCFG<2:0>: Automatic Pad and CRC Configuration bits

111 = All short frames will be zero-padded to 64 bytes and a valid CRC will then be appended
110 = No automatic padding of short frames
101 = MAC will automatically detect VLAN Protocol frames which have a 8100h type field and automatically pad to 64 bytes. If the frame is not a VLAN frame, it will be padded to 60 bytes. After padding, a valid CRC will be appended.
100 = No automatic padding of short frames
011 = All short frames will be zero-padded to 64 bytes and a valid CRC will then be appended
010 = No automatic padding of short frames
001 = All short frames will be zero-padded to 60 bytes and a valid CRC will then be appended
000 = No automatic padding of short frames

bit 4 TXCRCEN: Transmit CRC Enable bit

1 = MAC will append a valid CRC to all frames transmitted regardless of PADCFG bits. TXCRCEN must be set if the PADCFG bits specify that a valid CRC will be appended.
0 = MAC will not append a CRC. The last 4 bytes will be checked and if it is an invalid CRC, it will be reported in the transmit status vector.

bit 3 PHDREN: Proprietary Header Enable bit

1 = Frames presented to the MAC contain a 4-byte proprietary header which will not be used when calculating the CRC
0 = No proprietary header is present. The CRC will cover all data (normal operation).

bit 2 HFRMEN: Huge Frame Enable bit

1 = Frames of any size will be allowed to be transmitted and received
0 = Frames bigger than MAMXFL will be aborted when transmitted or received

bit 1 FRMLNEN: Frame Length Checking Enable bit

1 = The type/length field of transmitted and received frames will be checked. If it represents a length, the frame size will be compared and mismatches will be reported in the transmit/receive status vector.
0 = Frame lengths will not be compared with the type/length field

bit 0 FULDPX: MAC Full-Duplex Enable bit

1 = MAC will operate in Full-Duplex mode. PDPXMD bit must also be set.
0 = MAC will operate in Half-Duplex mode. PDPXMD bit must also be clear.

REGISTER 6-3: MACON4: MAC CONTROL REGISTER 4

Legend:

• R = Readable bit
• W = Writable bit
• U = Unimplemented bit, read as ‘0’
• -n = Value at POR
• ‘1’ = Bit is set
• ‘0’ = Bit is cleared
• x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 DEFER: Defer Transmission Enable bit (applies to half duplex only)

• 1 = When the medium is occupied, the MAC will wait indefinitely for it to become free when attempting to transmit (use this setting for IEEE 802.3™ compliance)
• 0 = When the medium is occupied, the MAC will abort the transmission after the excessive deferral limit is reached

bit 5 BPEN: No Backoff During Backpressure Enable bit (applies to half duplex only)

• 1 = After incidentally causing a collision during backpressure, the MAC will immediately begin retransmitting
• 0 = After incidentally causing a collision during backpressure, the MAC will delay using the Binary Exponential Backoff algorithm before attempting to retransmit (normal operation)

bit 4 NOBKOFF: No Backoff Enable bit (applies to half duplex only)

• 1 = After any collision, the MAC will immediately begin retransmitting
• 0 = After any collision, the MAC will delay using the Binary Exponential Backoff algorithm before attempting to retransmit (normal operation)

bit 3-2 Unimplemented: Read as ‘0’

bit 1-0 Reserved: Maintain as ‘0’

REGISTER 6-4: MABBIPG: MAC BACK-TO-BACK INTER-PACKET GAP REGISTER

Legend:

• R = Readable bit
• W = Writable bit
• U = Unimplemented bit, read as ‘0’
• -n = Value at POR
• ‘1’ = Bit is set
• ‘0’ = Bit is cleared
• x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-0 BBIPG<6:0>: Back-to-Back Inter-Packet Gap Delay Time bits

When FULDPX (MACON3<0>) = 1: Nibble time offset delay between the end of one transmission and the beginning of the next in a back-to-back sequence. The register value should be programmed to the desired period in nibble times minus 3. The recommended setting is 15h which represents the minimum IEEE specified Inter-Packet Gap (IPG) of 9.6 µs.

When FULDPX (MACON3<0>) = 0: Nibble time offset delay between the end of one transmission and the beginning of the next in a back-to-back sequence. The register value should be programmed to the desired period in nibble times minus 6. The recommended setting is 12h which represents the minimum IEEE specified Inter-Packet Gap (IPG) of 9.6 µs.

DS39662E-page 36 © 2006-2012 Microchip Technology Inc.

6.6 PHY Initialization Settings

Depending on the application, bits in three of the PHY module’s registers may also require configuration.

The PHCON1.PDPXMD bit partially controls the device’s half/full-duplex configuration. Normally, this bit is initialized correctly by the external circuitry (see Section 2.6 “LED Configuration”). If the external circuitry is not present or incorrect, however, the host controller must program the bit properly. Alternatively, for an externally configurable system, the PDPXMD bit may be read and the FULDPX bit be programmed to match.

For proper duplex operation, the PHCON1.PDPXMD bit must also match the value of the MACON3.FULDPX bit.

If using half duplex, the host controller may wish to set the PHCON2.HDLDIS bit to prevent automatic loopback of the data which is transmitted.

The PHY register, PHLCON, controls the outputs of LEDA and LEDB. If an application requires a LED configuration other than the default, PHLCON must be altered to match the new requirements. The settings for LED operation are discussed in Section 2.6 “LED Configuration”. The PHLCON register is shown in Register 2-2 (page 9).

REGISTER 6-5: PHCON2: PHY CONTROL REGISTER 2

Legend:

bit 15 Unimplemented: Read as ‘0’

bit 14 FRCLNK: PHY Force Linkup bit
1 = Force linkup even when no link partner is detected
0 = Normal operation

bit 13 TXDIS: Twisted-Pair Transmitter Disable bit
1 = Disable twisted-pair transmitter
0 = Normal operation

bit 12-11 Reserved: Write as ‘0’

bit 10 JABBER: Jabber Correction Disable bit
1 = Disable jabber correction
0 = Normal operation

bit 9 Reserved: Write as ‘0’

bit 8 HDLDIS: PHY Half-Duplex Loopback Disable bit
When PHCON1<8> = 1 or PHCON1<14> = 1:
This bit is ignored.
When PHCON1<8> = 0 and PHCON1<14> = 0:
1 = Transmitted data will only be sent out on the twisted-pair interface
0 = Transmitted data will be looped back to the MAC and sent out on the twisted-pair interface

bit 7-0 Reserved: Write as ‘0’

NOTES:

.

7.0 TRANSMITTING AND RECEIVING PACKETS

7.1 Transmitting Packets

The MAC inside the ENC28J60 will automatically generate the preamble and Start-of-Frame delimiter fields when transmitting. Additionally, the MAC can generate any padding (if needed) and the CRC if configured to do so. The host controller must generate and write all other frame fields into the buffer memory for transmission.

Additionally, the ENC28J60 requires a single per packet control byte to precede the packet for transmission. The per packet control byte is organized as shown in Figure 7-1. Before transmitting packets, the MAC registers which alter the transmission characteristics should be initialized as documented in Section 6.0 “Initialization”.

For an example of how the entire transmit packet and results will look in memory, see Figure 7-2.

FIGURE 7-1: FORMAT FOR PER PACKET CONTROL BYTES

bit 7-4 Unused

bit 3 PHUGEEN: Per Packet Huge Frame Enable bit

When POVERRIDE = 1:

1 = The packet will be transmitted in whole

0 = The MAC will transmit up to the number of bytes specified by MAMXFL; if the packet is larger than MAMXFL, it will be aborted after MAMXFL is reached

When POVERRIDE = 0:

This bit is ignored.

bit 2 PPADEN: Per Packet Padding Enable bit

When POVERRIDE = 1:

1 = The packet will be zero-padded to 60 bytes if it is less than 60 bytes

0 = The packet will be transmitted without adding any padding bytes

When POVERRIDE = 0:

This bit is ignored.

bit 1 PCRCEN: Per Packet CRC Enable bit

When POVERRIDE = 1:

1 = A valid CRC will be calculated and attached to the frame

0 = No CRC will be appended; the last 4 bytes of the frame will be checked for validity as a CRC.

When POVERRIDE = 0:

This bit is ignored.

bit 0 POVERRIDE: Per Packet Override bit

1 = The values of PCRCEN, PPADEN and PHUGEEN will override the configuration defined by MACON3

0 = The values in MACON3 will be used to determine how the packet will be transmitted

FIGURE 7-2: SAMPLE TRANSMIT PACKET LAYOUT

PHUGEEN, PPADN, PCRCEN and POVERRIDE

Destination Address, Source Address, Type/Length and Data

Status Vector Written by the Hardware

To achieve the example layout shown in Figure 7-2 and to transmit a packet, the host controller should:

1. Appropriately program the ETXST Pointer to point to an unused location in memory. It will point to the per packet control byte. In the example, it would be programmed to 0120h. It is recommended that an even address be used for ETXST.

2. Use the WBM SPI command to write the per packet control byte, the destination address, the source MAC address, the type/length and the data payload.

3. Appropriately program the ETXND Pointer. It should point to the last byte in the data payload. In the example, it would be programmed to 0156h.

4. Clear EIR.TXIF, set EIE.TXIE and set EIE.INTIE to enable an interrupt when done (if desired).

5. Start the transmission process by setting ECON1.TXRTS.

If a DMA operation was in progress while the TXRTS bit was set, the ENC28J60 will wait until the DMA operation is complete before attempting to transmit the packet. This possible delay is required because the DMA and transmission engine share the same memory access port. Similarly, if the DMAST bit in ECON1 is set after TXRTS is already set, the DMA will wait until the TXRTS bit becomes clear before doing anything. While the transmission is in progress, none of the unshaded bits (except for the ECON1 register’s bits) in Table 7-2 should be changed. Additionally, none of the bytes to be transmitted should be read or written to through the SPI. If the host controller wishes to cancel the transmission, it can clear the TXRTS bit.

When the packet is finished transmitting or is aborted due to an error/cancellation, the ECON1.TXRTS bit will be cleared, a seven-byte transmit status vector will be written to the location pointed to by ETXND + 1, the EIR.TXIF will be set and an interrupt will be generated (if enabled). The ETXST and ETXND Pointers will not be modified. To check if the packet was successfully transmitted, the ESTAT.TXABRT bit should be read. If it was set, the host controller may interrogate the ESTAT.LATECOL bit in addition to the various fields in the transmit status vector to determine the cause. The transmit status vector is organized as shown in Table 7-1. Multi-byte fields are written in little-endian format.

TABLE 7-1: TRANSMIT STATUS VECTORS

TABLE 7-2: SUMMARY OF REGISTERS USED FOR PACKET TRANSMISSION

Legend: — = unimplemented, r = reserved bit. Shaded cells are not used.

Note 1: CLKRDY resets to ‘0’ on a Power-on Reset but is unaffected on all other Resets.

DS39662E-page 42 © 2006-2012 Microchip Technology Inc.

7.2 Receiving Packets

7.2.1 ENABLING RECEPTION

Assuming that the receive buffer has been initialized, the MAC has been properly configured and the receive filters have been configured to receive Ethernet packets, the host controller should:

1. If an interrupt is desired whenever a packet is received, set EIE.PKTIE and EIE.INTIE.
2. If an interrupt is desired whenever a packet is dropped due to insufficient buffer space, clear EIR.RXERIF and set both EIE.RXERIE and EIE.INTIE
3. Enable reception by setting ECON1.RXEN.

After setting RXEN, the Duplex mode and the Receive Buffer Start and End Pointers should not be modified. Additionally, to prevent unexpected packets from arriving, it is recommended that RXEN be cleared before altering the receive filter configuration (ERXFCON) and MAC address.

After reception is enabled, packets which are not filtered out will be written into the circular receive buffer. Any packet which does not meet the necessary filter criteria will be discarded and the host controller will not have any means of identifying that a packet was thrown away. When a packet is accepted and completely written into the buffer, the EPKTCNT register will increment, the EIR.PKTIF bit will be set, an interrupt will be generated (if enabled) and the Hardware Write Pointer, ERXWRPT, will automatically advance.

7.2.2 RECEIVE PACKET LAYOUT

Figure 7-3 shows the layout of a received packet. The packets are preceded by a six-byte header which contains a Next Packet Pointer, in addition to a receive status vector which contains receive statistics, including the packet's size. This receive status vector is shown in Table 7-3.

If the last byte in the packet ends on an odd value address, the hardware will automatically add a padding byte when advancing the Hardware Write Pointer. As such, all packets will start on an even boundary.

FIGURE 7-3: SAMPLE RECEIVE PACKET LAYOUT

TABLE 7-3: RECEIVE STATUS VECTORS

7.2.3 READING RECEIVED PACKETS

To process the packet, the host controller will normally use the RBM SPI command and start reading from the beginning of the next Packet Pointer. The host controller will save the next Packet Pointer, any necessary bytes from the receive status vector and then proceed to read the actual packet contents. If ECON2.AUTOINC is set, it will be able to sequentially read the entire packet without ever modifying the ERDPT registers. The Read Pointer would automatically wrap at the end of the circular receive buffer to the beginning.

In the event that the application needed to do random access to the packet, it would be necessary to manually calculate the proper ERDPT, taking care to not exceed the end of the receive buffer if the packet spans the ERXND-to-ERXST buffer boundary. In other words, given the packet start address and a desired offset, the application should follow the logic shown in Example 7-1.

EXAMPLE 7-1: RANDOM ACCESS ADDRESS CALCULATION

if Packet Start Address + Offset > ERXND, then ERDPT = Packet Start Address + Offset – (ERXND – ERXST + 1) else ERDPT = Packet Start Address + Offset

7.2.4 FREEING RECEIVE BUFFER SPACE

After the host controller has processed a packet (or part of the packet) and wishes to free the buffer space used by the processed data, the host controller must advance the Receive Buffer Read Pointer, ERXRDPT. The ENC28J60 will always write up to, but not including, the memory pointed to by the Receive Buffer Read Pointer. If the ENC28J60 ever attempts to overwrite the Receive Buffer Read Pointer location, the packet in progress will be aborted, the EIR.RXERIF will be set and an interrupt will be generated (if enabled). In this manner, the hardware will never overwrite unprocessed packets. Normally, the ERXRDPT will be advanced to the value pointed to by the next Packet Pointer which precedes the receive status vector for the current packet. Following such a procedure will not require any pointer calculations to account for wrapping at the end of the circular receive buffer.

The Receive Buffer Read Pointer Low Byte (ERXRDPTL register) is internally buffered to prevent the pointer from moving when only one byte is updated through the SPI. To move ERXRDPT, the host controller must write to ERXRDPTL first. The write will update the internal buffer but will not affect the register. When the host controller writes to ERXRDPTH, the internally buffered low byte will be loaded into the ERXRDPTL register at the same time. The ERXRDPT bytes can be read in any order. When they are read, the actual value of the registers will be returned. As a result, the buffered low byte is not readable.

In addition to advancing the Receive Buffer Read Pointer, after each packet is fully processed, the host controller must write a '1' to the ECON2.PKTDEC bit. Doing so will cause the EPKTCNT register to decrement by 1. After decrementing, if EPKTCNT is '0', the EIR.PKTIF flag will automatically be cleared. Otherwise, it will remain set, indicating that additional packets are in the receive buffer and are waiting to be processed. Attempts to decrement EPKTCNT below 0 are ignored. Additionally, if the EPKTCNT register ever maximizes at 255, all new packets which are received will be aborted, even if buffer space is available. To indicate the error, the EIR.RXERIF will be set and an interrupt will be generated (if enabled). To prevent this condition, the host controller must properly decrement the counter whenever a packet is processed.

Because only one pointer is available to control buffer area ownership, the host controller must process packets in the order they are received. If the host controller wishes to save a packet to be processed later, it should copy the packet to an unused location in memory. It may accomplish this efficiently using the integrated DMA controller (see Section 13.0 "Direct Memory Access Controller").

7.2.5 RECEIVE BUFFER FREE SPACE

At any time the host controller wishes to know how much receive buffer space is remaining, it should read the Hardware Write Pointer (ERXWRPT registers) and compare it with the ERXRDPT registers. Combined with the known size of the receive buffer, the free space can be derived.

Note: The ERXWRPT registers only update when a packet has been successfully received. If the host controller reads it just before another packet is to be successfully completed, the value returned could be stale and off by the maximum frame length permitted (MAMXFL) plus 7. Furthermore, as the host controller reads one byte of ERXWRPT, a new packet may arrive and update the pointer before the host controller has an opportunity to read the other byte of ERXWRPT.

When reading the ERXWRPT register with the receive hardware enabled, special care must be taken to ensure the low and high bytes are read as a matching set.

To be assured that a matching set is obtained:

1. Read the EPKTCNT register and save its contents.
2. Read ERXWRPTL and ERXWRPTH.
3. Read the EPKTCNT register again.
4. Compare the two packet counts. If they are not the same, go back to Step 2.

With the Hardware Write Pointer obtained, the free space can be calculated as shown in Example 7-2. The hardware prohibits moving the Write Pointer to the same value occupied by ERXRDPT (except when the Buffer Pointers are being configured), so at least one byte will always go unused in the buffer. The example calculation reflects the lost byte.

EXAMPLE 7-2: RECEIVE BUFFER FREE SPACE CALCULATION if ERXWRPT > ERXRDPT, then Free Space = (ERXND – ERXST) – (ERXWRPT – ERXRDPT) else if ERXWRPT = ERXRDPT, then Free Space = (ERXND – ERXST) else Free Space = ERXRDPT – ERXWRPT – 1

TABLE 7-4: SUMMARY OF REGISTERS USED FOR PACKET RECEPTION

Legend: — = unimplemented, r = reserved bit. Shaded cells are not used.

Note 1: CLKRDY resets to ‘0’ on a Power-on Reset but is unaffected on all other Resets.