Microchip ENC28J60 datasheet: 8.0 Receive filters

8.0 RECEIVE FILTERS

To minimize the processing requirements of the host controller, the ENC28J60 incorporates several different receive filters which can automatically reject packets which are not needed. Six different types of packet filters are implemented:

• Unicast

• Pattern Match

• Magic Packet™

• Hash Table

• Multicast

• Broadcast

The individual filters are all configured by the ERXFCON register (Register 8-1). More than one filter can be active at any given time. Additionally, the filters can be configured by the ANDOR bit to either logically AND, or logically OR, the tests of several filters. In other words, the filters may be set so that only packets accepted by all active filters are accepted, or a packet accepted by any one filter is accepted. The flowcharts in Figure 8-1 and Figure 8-2 show the effect that each of the filters will have depending on the setting of ANDOR.

The device can enter Promiscuous mode and receive all packets by clearing the ERXFCON register. The proper setting of the register will depend on the application requirements.

REGISTER 8-1: ERXFCON: ETHERNET RECEIVE FILTER CONTROL REGISTER

Legend:

R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 7
UCEN: Unicast Filter Enable bit
When ANDOR = 1:
1 = Packets not having a destination address matching the local MAC address will be discarded
0 = Filter disabled
When ANDOR = 0:
1 = Packets with a destination address matching the local MAC address will be accepted
0 = Filter disabled

bit 6
ANDOR: AND/OR Filter Select bit
1 = AND: Packets will be rejected unless all enabled filters accept the packet
0 = OR: Packets will be accepted unless all enabled filters reject the packet

bit 5
CRCEN: Post-Filter CRC Check Enable bit
1 = All packets with an invalid CRC will be discarded
0 = The CRC validity will be ignored

bit 4
PMEN: Pattern Match Filter Enable bit
When ANDOR = 1:
1 = Packets must meet the Pattern Match criteria or they will be discarded
0 = Filter disabled
When ANDOR = 0:
1 = Packets which meet the Pattern Match criteria will be accepted
0 = Filter disabled

bit 3
MPEN: Magic Packet™ Filter Enable bit
When ANDOR = 1:
1 = Packets must be Magic Packets for the local MAC address or they will be discarded
0 = Filter disabled
When ANDOR = 0:
1 = Magic Packets for the local MAC address will be accepted
0 = Filter disabled

bit 2
HTEN: Hash Table Filter Enable bit
When ANDOR = 1:
1 = Packets must meet the Hash Table criteria or they will be discarded
0 = Filter disabled
When ANDOR = 0:
1 = Packets which meet the Hash Table criteria will be accepted
0 = Filter disabled

bit 1
MCEN: Multicast Filter Enable bit
When ANDOR = 1:
1 = Packets must have the Least Significant bit set in the destination address or they will be discarded
0 = Filter disabled
When ANDOR = 0:
1 = Packets which have the Least Significant bit set in the destination address will be accepted
0 = Filter disabled

bit 0
BCEN: Broadcast Filter Enable bit
When ANDOR = 1:
1 = Packets must have a destination address of FF-FF-FF-FF-FF-FF or they will be discarded
0 = Filter disabled
When ANDOR = 0:
1 = Packets which have a destination address of FF-FF-FF-FF-FF-FF will be accepted
0 = Filter disabled

FIGURE 8-1: RECEIVE FILTERING USING OR LOGIC

Packet Detected on Wire, ANDOR = 0 (OR)

UCEN, PMEN, MPEN, HTEN, MCEN and BCEN all clear? Yes No

UCEN set? Yes Unicast packet? Yes CRCEN set? No No No

CRCEN valid? Yes Accept Packet No Reject Packet

PMEN set? Yes Pattern matches? Yes No No

MPEN set? Yes Magic Packet™ for us? Yes No No

HTEN set? Yes Hash table bit set? Yes No No

MCEN set? Yes Multicast destination? Yes No No

BCEN set? Yes Broadcast destination? Yes No No

FIGURE 8-2: RECEIVE FILTERING USING AND LOGIC

Packet Detected on Wire ANDOR = 1 (AND)

├─> UCEN set? │ ├─ Yes ──> Unicast packet? │ │ ├─ No ────────────────────────────────────────────────────────────────┐ │ │ └─ Yes ──────────────────────────────────────────────────────────────┤ │ └─ No ───────────────────────────────────────────────────────────────────────┤ │ │ ├─> PMEN set? │ │ ├─ Yes ──> Pattern matches? │ │ │ ├─ No ────────────────────────────────────────────────────────────────┤ │ │ └─ Yes ──────────────────────────────────────────────────────────────┤ │ └─ No ───────────────────────────────────────────────────────────────────────┤ │ │ ├─> MPEN set? │ │ ├─ Yes ──> Magic Packet™ for us? │ │ │ ├─ No ────────────────────────────────────────────────────────────────┤ │ │ └─ Yes ───────────────────────────────────────────────────────────────┤ │ └─ No ────────────────────────────────────────────────────────────────────────┤ │ │ ├─> HTEN set? │ │ ├─ Yes ──> Hash Table bit set? │ │ │ ├─ No ────────────────────────────────────────────────────────────────┤ │ │ └─ Yes ───────────────────────────────────────────────────────────────┤ │ └─ No ────────────────────────────────────────────────────────────────────────┤ │ │ ├─> MCEN set? │ │ ├─ Yes ──> Multicast destination? │ │ │ ├─ No ────────────────────────────────────────────────────────────────┤ │ │ └─ Yes ───────────────────────────────────────────────────────────────┤ │ └─ No ────────────────────────────────────────────────────────────────────────┤ │ │ ├─> BCEN set? │ │ ├─ Yes ──> Broadcast destination? │ │ │ ├─ No ────────────────────────────────────────────────────────────────┤ │ │ └─ Yes ───────────────────────────────────────────────────────────────┤ │ └─ No ────────────────────────────────────────────────────────────────────────┤ │ │ ├─> CRCEN set? │ │ ├─ No ──────────────────────────────────────────────────────────────────────┼─> Accept Packet │ └─ Yes ──> CRC valid? │ │ ├─ No ───────────────────────────────────────────────────────────────┼─> Reject Packet │ └─ Yes ──────────────────────────────────────────────────────────────┘

DS39662E-page 50 . © 2006-2012 Microchip Technology Inc.

8.1 Unicast Filter

The Unicast receive filter checks the destination address of all incoming packets. If the destination address exactly matches the contents of the MAADR registers, the packet will meet the Unicast filter criteria.

8.2 Pattern Match Filter

The Pattern Match filter selects up to 64 bytes from the incoming packet and calculates an IP checksum of the bytes. The checksum is then compared to the EPMCS registers. The packet meets the Pattern Match filter criteria if the calculated checksum matches the EPMCS registers. The Pattern Match filter may be useful for filtering packets which have expected data inside them.

To use the Pattern Match filter, the host controller must program the Pattern Match offset (EPMOH:EPMOL), all of the Pattern Match mask bytes (EPMM7:EPMM0) and the Pattern Match Checksum register pair (EPMCSH:EPMCSL). The Pattern Match offset should be loaded with the offset from the beginning of the destination address field to the 64-byte window which will be used for the checksum computation. Within the 64-byte window, each individual byte can be selectively included or excluded from the checksum computation by setting or clearing the respective bit in the Pattern Match mask. If a packet is received which would cause the 64-byte window to extend past the end of the CRC, the filter criteria will immediately not be met, even if the corresponding mask bits are all '0'. The Pattern Match Checksum registers should be programmed to the checksum which is expected for the selected bytes. The checksum is calculated in the same manner that the DMA module calculates checksums (see Section 13.2 "Checksum Calculations"). Data bytes which have corresponding mask bits programmed to '0' are completely removed for purposes of calculating the checksum, as opposed to treating the data bytes as zero.

As an example, if the application wished to filter all packets having a particular source MAC address of 00-04-A3-FF-FF-FF, it could program the Pattern Match offset to 0000h and then set bits 6 and 7 of EPMM0 and bits 0, 1, 2 and 3 of EPMM1 (assuming all other mask bits are '0'). The proper checksum to program into the EPMCS registers would be 0x5BFC. As an alternative configuration, it could program the offset to 0006h and set bits 0, 1, 2, 3, 4 and 5 of EPMM0. The checksum would still be 5BFCh. However, the second case would be less desirable as packets less than 70 bytes long could never meet the Pattern Match criteria, even if they would generate the proper checksum given the mask configuration.

Another example of a Pattern Matching filter is illustrated in Figure 8-3.

FIGURE 8-3: SAMPLE PATTERN MATCH FORMAT

8.3 Magic Packet™ Filter

The Magic Packet filter checks the destination address and data fields of all incoming packets. If the destination address matches the MAADR registers and the data field holds a valid Magic Packet pattern someplace within it, then the packet will meet the Magic Packet filter criteria. The Magic Packet pattern consists of a sync pattern of six 0xFF bytes, followed by 16 repeats of the destination address. See Figure 8-4 for a sample Magic Packet.

FIGURE 8-4: SAMPLE MAGIC PACKET™ FORMAT

8.4 Hash Table Filter

The Hash Table receive filter performs a CRC over the six destination address bytes in the packet. The CRC is then used as a pointer into the bits of the EHT registers. If the pointer points to a bit which is set, the packet meets the Hash Table filter criteria. For example, if the CRC is calculated to be 0x5, bit 5 in the Hash Table will be checked. If it is set, the Hash Table filter criteria will be met. If every bit is clear in the Hash Table, the filter criteria will never be met. Similarly, if every bit is set in the Hash Table, the filter criteria will always be met.

8.5 Multicast Filter

The Multicast receive filter checks the destination address of all incoming packets. If the Least Significant bit of the first byte of the destination address is set, the packet will meet the Multicast filter criteria.

8.6 Broadcast Filter

The Broadcast receive filter checks the destination address of all incoming packets. If the destination address is FF-FF-FF-FF-FF-FF, the packet will meet the Broadcast filter criteria.

9.0 DUPLEX MODE CONFIGURATION AND NEGOTIATION

The ENC28J60 does not support automatic duplex negotiation. If it is connected to an automatic duplex negotiation enabled network switch or Ethernet controller, the ENC28J60 will be detected as a half-duplex device. To communicate in Full-Duplex mode, the ENC28J60 and the remote node (switch, router or Ethernet controller) must be manually configured for full-duplex operation.

9.1 Half-Duplex Operation

The ENC28J60 operates in Half-Duplex mode when MACON3.FULDPX = 0 and PHCON1.PDPXMD = 0. If only one of these two bits is set, the ENC28J60 will be in an indeterminate state and not function correctly. Since switching between Full and Half-Duplex modes may result in this indeterminate state, the host controller should not transmit any packets (maintain ECON1.TXRTS clear) and packet reception should be disabled (ECON1.RXEN and ESTAT.RXBUSY should be clear) during this period.

In Half-Duplex mode, only one Ethernet controller may be transmitting on the physical medium at any time. If the host controller sets the ECON1.TXRTS bit, requesting that a packet be transmitted while another Ethernet controller is already transmitting, the ENC28J60 will delay, waiting for the remote transmitter to stop. After the transmission stops, the ENC28J60 will attempt to transmit its packet. If another Ethernet controller starts transmitting at approximately the same time that the ENC28J60 starts transmitting, the data on the wire will become corrupt and a collision will occur. The hardware will handle this condition in one of two ways:

1. If the collision occurs before the number of bytes specified by the “Collision Window” in MACLCON2 were transmitted, the ECON1.TXRTS bit will remain set, a random exponential back off delay will elapse as defined by the IEEE 802.3 specification and then a new attempt to transmit the packet from the beginning will occur. The host controller will not need to intervene. If the number of retransmission attempts already matches the “Retransmission Maximum” (RETMAX) defined in MACLCON1, the packet will be aborted and ECON1.TXRTS will be cleared. The host controller will then be responsible for taking appropriate action. The host controller will be able to determine that the packet was aborted instead of being successfully transmitted by reading the ESTAT.TXABRT flag. For more information, see Section 7.1 “Transmitting Packets”. A transmit abort will cause the transmit error interrupt.

2. If the collision occurs after the number of bytes specified by the “Collision Window” in MACLCON2 were transmitted, the packet will be immediately aborted without any retransmission attempts. Ordinarily, in IEEE 802.3 compliant networks which are properly configured, this late collision will not occur. User intervention may be required to correct the issue. This problem may occur as a result of a full-duplex node attempting to transmit on the half-duplex medium. Alternatively, the ENC28J60 may be attempting to operate in Half-Duplex mode while it may be connected to a full-duplex network. Excessively long cabling and network size may also be a possible cause of late collisions.

When set in Half-Duplex mode, the Reset default configuration will loop transmitted packets back to itself. Unless the receive filter configuration filters these packets out, they will be written into the circular receive buffer, just as any other network traffic. To stop this behavior, the host controller should set the PHCON2.HLDIS bit.

9.2 Full-Duplex Operation

The ENC28J60 operates in Full-Duplex mode when MACON3.FULDPX = 1 and PHCON1.PDPXMD = 1. If only one of these two bits is clear, the ENC28J60 will be in an indeterminate state and not function correctly. Since switching between Full and Half-Duplex modes may result in this indeterminate state, the host controller should not transmit any packets (maintain ECON1.TXRTS clear) and packet reception should be disabled (ECON1.RXEN and ESTAT.RXBUSY should be clear) during this period.

In Full-Duplex mode, packets will be transmitted simultaneously while packets may be received. Given this, it is impossible to cause any collisions when transmitting packets. Several configuration fields, such as “Retransmission Maximum” (RETMAX) in MACLCON1 and “Collision Window” (COLWIN) in MACLCON2, will not be used.

When set in Full-Duplex mode, the Reset default configuration will not loop transmitted packets back to itself. If loopback is desired for diagnostic purposes, the PHCON1.PLOOPBK bit should be set by the host controller. Enabling loopback in Full-Duplex mode will disable the twisted-pair output driver and ignore all incoming data, thus dropping any link (if established). All packets received as a result of the loopback configuration will be subject to all enabled receive filters, just as ordinary network traffic would be.

NOTES:

DS39662E-page 54 . © 2006-2012 Microchip Technology Inc.

10.0 FLOW CONTROL

The ENC28J60 implements hardware flow control for both Full and Half-Duplex modes. The operation of this feature differs depending on which mode is being used.

10.1 Half-Duplex Mode

In Half-Duplex mode, setting the EFLOCON.FCEN0 bit causes flow control to be enabled. When FCEN0 is set, a continuous preamble pattern of alternating ‘1’s and ‘0’s (55h) will automatically be transmitted on the Ethernet medium. Any connected nodes will see the transmission and either not transmit anything, waiting for the ENC28J60’s transmission to end, or will attempt to transmit and immediately cause a collision. Because a collision will always occur, no nodes on the network will be able to communicate with each other and no new packets will arrive.

When the host controller tells the ENC28J60 to transmit a packet by setting ECON1.TXRTS, the preamble pattern will stop being transmitted. An Inter-Packet Gap delay will pass as configured by register MABBIPG and then the ENC28J60 will attempt to transmit its packet. During the Inter-Packet Gap delay, other nodes may begin to transmit. Because all traffic was jammed previously, several nodes may begin transmitting and a series of collisions may occur. When the ENC28J60 successfully finishes transmitting its packet or aborts it, the transmission of the preamble pattern will automatically restart. When the host controller wishes to no longer jam the network, it should clear the FCEN0 bit. The preamble transmission will cease and normal network operation will resume.

Given the detrimental network effects that are possible and lack of effectiveness, it is not recommended that half-duplex flow control be used unless the application will be in a closed network environment with proper testing.

10.2 Full-Duplex Mode

In Full-Duplex mode (MACON3.FULDPX = 1), hardware flow control is implemented by means of transmitting pause control frames as defined by the IEEE 802.3 specification. Pause control frames are 64-byte frames consisting of the reserved Multicast destination address of 01-80-C2-00-00-01, the source address of the sender, a special pause opcode, a 2-byte pause timer value and padding/CRC.

Normally, when a pause control frame is received by a MAC, the MAC will finish the packet it is transmitting and then stop transmitting any new frames. The pause timer value will be extracted from the control frame and used to initialize an internal timer. The timer will automatically decrement every 512 bit times or 51.2 µs. While the timer is counting down, reception of packets is still enabled. If new pause frames arrive, the timer will be reinitialized with the new pause timer value. When the timer reaches zero or was sent a frame with a zero pause timer value, the MAC that received the pause frame will resume transmitting any pending packets. To prevent a pause frame from stopping all traffic on the entire network, Ethernet switches and routers do not propagate pause control frames in Full-Duplex mode. The pause operation only applies to the recipient.

A sample network is shown in Figure 10-1. If Computer A were to be transmitting too much data to the ENC28J60 in Full-Duplex mode, the ENC28J60 could transmit a pause control frame to stop the data which is being sent to it. The Ethernet switch would take the pause frame and stop sending data to the ENC28J60. If Computer A continues to send data, the Ethernet switch will buffer the data so it can be transmitted later when its pause timer expires. If the Ethernet switch begins to run out of buffer space, it will likely transmit a pause control frame of its own to Computer A. If, for some reason, the Ethernet switch does not generate a pause control frame of its own, or one of the nodes does not properly handle the pause frame it receives, then packets will inevitably be dropped. In any event, any communication between Computer A and Computer B will always be completely unaffected.

FIGURE 10-1: SAMPLE FULL-DUPLEX NETWORK

To enable flow control on the ENC28J60 in Full-Duplex mode, the host controller must set the TXPAUS and RXPAUS bits in the MACON1 register. Then, at any time that the receiver buffer is running out of space, the host controller should turn flow control on by writing the value 02h to the EFLOCON register. The hardware will periodically transmit pause frames loaded with the pause timer value specified in the EPAUS registers. The host controller can continue to transmit its own packets without interfering with the flow control hardware.

When space has been made available for more packets in the receive buffer, the host controller should turn flow control off by writing the value 03h to the EFLOCON register. The hardware will send one last pause frame loaded with a pause timer value of 0000h. When the pause frame is received by the remote node, it will resume normal network operations.

When RXPAUS is set in the MACON1 register and a valid pause frame arrives with a non-zero pause timer value, the ENC28J60 will automatically inhibit transmissions. If the host controller sets the ECON1.TXRTS bit to send a packet, the hardware will simply wait until the pause timer expires before attempting to send the packet and subsequently clearing the TXRTS bit. Normally, the host controller will never know that a pause frame has been received. However, if it is desirable to the host controller to know when the MAC is paused or not, it should set the PASSALL bit in MACON1 and then manually interpret the pause control frames which may arrive.

REGISTER 10-1: EFLOCON: ETHERNET FLOW CONTROL REGISTER

Legend:

R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2 FULDPXS: Read-Only MAC Full-Duplex Shadow bit
1 = MAC is configured for Full-Duplex mode, FULDPX (MACON3<0>) is set
0 = MAC is configured for Half-Duplex mode, FULDPX (MACON3<0>) is clear

bit 1-0 FCEN<1:0>: Flow Control Enable bits

When FULDPXS = 1:
11 = Send one pause frame with a ‘0’ timer value and then turn flow control off
10 = Send pause frames periodically
01 = Send one pause frame then turn flow control off
00 = Flow control off

When FULDPXS = 0:
11 = Flow control on
10 = Flow control off
01 = Flow control on
00 = Flow control off

TABLE 10-1: SUMMARY OF REGISTERS USED WITH FLOW CONTROL

\begin{tabular}{|l|c|c|c|c|c|c|c|c|l|} \hline Name & Bit 7 & Bit 6 & Bit 5 & Bit 4 & Bit 3 & Bit 2 & Bit 1 & Bit 0 & Reset Values on page \ \hline ECON1 & TXRST & RXRST & DMAST & CSUMEN & TXRTS & RXEN & BSEL1 & BSEL0 & 13 \ \hline MACON1 & — & — & — & r & TXPAUS & RXPAUS & PASSALL & MARXEN & 14 \ \hline MABBIPG & \multicolumn{8}{l|}{Back-to-Back Inter-Packet Gap (BBIPG<6:0>)} & 14 \ \hline EFLOCON & — & — & — & — & — & FULDPXS & FCEN1 & FCEN0 & 14 \ \hline EPAUSL & \multicolumn{8}{l|}{Pause Timer Value Low Byte (EPAUS<7:0>)} & 14 \ \hline EPAUSH & \multicolumn{8}{l|}{Pause Timer Value High Byte (EPAUS<15:8>)} & 14 \ \hline \end{tabular}

Legend: r = reserved, — = unimplemented, read as '0'. Shaded cells are not used.

NOTES:

DS39662E-page 58 . © 2006-2012 Microchip Technology Inc.

11.0 RESET

The ENC28J60 differentiates between various kinds of Reset:

• Power-on Reset (POR)
• System Reset
• Transmit Only Reset
• Receive Only Reset
• Miscellaneous MAC and PHY Subsystem Resets

A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 11-1.

FIGURE 11-1: ON-CHIP RESET CIRCUIT

11.1 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation.

The POR circuitry is always enabled. As a result, most applications do not need to attach any external circuitry to the \overlineRESET pin to ensure a proper Reset at power-up. The \overlineRESET pin's internal weak pull-up will maintain a logical high level on the pin during normal device operation.

To ensure proper POR operation, a minimum rise rate for VDD is specified (Parameter D003). The application circuit must meet this requirement to allow the Oscillator Start-up Timer and CLKOUT functions to reset properly.

After a Power-on Reset, the contents of the dual port buffer memory will be unknown. However, all registers will be loaded with their specified Reset values. Certain portions of the ENC28J60 must not be accessed immediately after a POR. See Section 2.2 “Oscillator Start-up Timer” for more information.

11.2 System Reset

The System Reset of ENC28J60 can be accomplished by either the \overlineRESET pin, or through the SPI interface. The \overlineRESET pin provides an asynchronous method for triggering an external Reset of the device. A Reset is generated by holding the \overlineRESET pin low. The ENC28J60 has a noise filter in the \overlineRESET path which detects and ignores small pulses of time, tRSTLOW, or less. When the \overlineRESET pin is held high, the ENC28J60 will operate normally.

The ENC28J60 can also be reset via the SPI using the System Reset Command. See Section 4.0 “Serial Peripheral Interface (SPI)”.

The \overlineRESET pin will not be driven low by any internal Resets, including a System Reset command via the SPI interface.

After a System Reset, all PHY registers should not be read or written to until at least 50 µs have passed since the Reset has ended. All registers will revert to their Reset default values. The dual port buffer memory will maintain state throughout the System Reset.

11.3 Transmit Only Reset

The Transmit Only Reset is performed by writing a ‘1’ to the TXRST bit in the ECON1 register using the SPI interface. If a packet was being transmitted when the TXRST bit was set, the hardware will automatically clear the TXRTS bit and abort the transmission. This action resets the transmit logic only. The System Reset automatically performs the Transmit Only Reset. Other register and control blocks, such as buffer management and host interface, are not affected by a Transmit Only Reset event. When the host controller wishes to return to normal operation, it should clear the TXRST bit.

11.4 Receive Only Reset

The Receive Only Reset is performed by writing a ‘1’ to the RXRST bit in the ECON1 register using the SPI interface. If packet reception was enabled (the RXEN bit was set) when RXRST was set, the hardware will automatically clear the RXEN bit. If a packet was being received, it would be immediately aborted. This action resets receive logic only. The System Reset automatically performs Receive Only Reset. Other register and control blocks, such as the buffer management and host interface blocks, are not affected by a Receive Only Reset event. When the host controller wishes to return to normal operation, it should clear the RXRST bit.

11.5 PHY Subsystem Reset

The PHY module may be reset by writing a ‘1’ to the PRST bit in the PHCON1 register (Register 11-1). All the PHY register contents will revert to their Reset defaults. Unlike other Resets, the PHY cannot be removed from Reset immediately after setting PRST. The PHY requires a delay, after which the hardware automatically clears the PRST bit. After a Reset is issued, the host controller should poll PRST and wait for it to become clear before using the PHY.

REGISTER 11-1: PHCON1: PHY CONTROL REGISTER 1

bit 15 PRST: PHY Software Reset bit 1 = PHY is processing a Software Reset (automatically resets to ‘0’ when done) 0 = Normal operation

bit 14 PLOOPBK: PHY Loopback bit 1 = All data transmitted will be returned to the MAC. The twisted-pair interface will be disabled. 0 = Normal operation

bit 13-12 Unimplemented: Read as ‘0’

bit 11 PPWRSV: PHY Power-Down bit 1 = PHY is shut down 0 = Normal operation

bit 10 Reserved: Maintain as ‘0’

bit 9 Unimplemented: Read as ‘0’

bit 8 PDPXMD: PHY Duplex Mode bit(1) 1 = PHY operates in Full-Duplex mode 0 = PHY operates in Half-Duplex mode

bit 7 Reserved: Maintain as ‘0’

bit 6-0 Unimplemented: Read as ‘0’

Note 1: Reset values of the Duplex mode/status bits depend on the connection of the LED to the LEDB pin (see Section 2.6 “LED Configuration” for additional details).

NOTES:

DS39662E-page 62 . © 2006-2012 Microchip Technology Inc.