Microchip ENC28J60 datasheet: 12.0 interrupts

12.0 interrupts

The ENC28J60 has multiple interrupt sources and an interrupt output pin to signal the occurrence of events to the host controller. The interrupt pin is designed for use by a host controller that is capable of detecting falling edges.

Interrupts are managed with two registers. The EIE register contains the individual interrupt enable bits for each interrupt source, while the EIR register contains the corresponding interrupt flag bits. When an interrupt occurs, the interrupt flag is set. If the interrupt is enabled in the EIE register and the INTIE global interrupt enable bit is set, the \overlineINT pin will be driven low (see Figure 12-1).

Note: Except for the LINKIF interrupt flag, interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the associated global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.

When an enabled interrupt occurs, the interrupt pin will remain low until all flags which are causing the interrupt are cleared or masked off (enable bit is cleared) by the host controller. If more than one interrupt source is enabled, the host controller must poll each flag in the EIR register to determine the source(s) of the interrupt. It is recommended that the Bit Field Clear (BFC) SPI command be used to reset the flag bits in the EIR register rather than the normal Write Control Register (WCR) command. This is necessary to prevent unintentionally altering a flag that changes during the write command. The BFC and WCR commands are discussed in detail in Section 4.0 "Serial Peripheral Interface (SPI)".

After an interrupt occurs, the host controller should clear the global enable bit for the interrupt pin before servicing the interrupt. Clearing the enable bit will cause the interrupt pin to return to the non-asserted state (high). Doing so will prevent the host controller from missing a falling edge should another interrupt occur while the immediate interrupt is being serviced. After the interrupt has been serviced, the global enable bit may be restored. If an interrupt event occurred while the previous interrupt was being processed, the act of resetting the global enable bit will cause a new falling edge on the interrupt pin to occur.

FIGURE 12-1: ENC28J60 INTERRUPT LOGIC

12.1 INT Interrupt Enable (INTIE)

The INT Interrupt Enable bit (INTIE) is a global enable bit which allows the following interrupts to drive the \overlineINT pin:

• Receive Error Interrupt (RXERIF)
• Transmit Error Interrupt (TXERIF)
• Transmit Interrupt (TXIF)
• Link Change Interrupt (LINKIF)
• DMA Interrupt (DMAIF)
• Receive Packet Pending Interrupt (PKTIF)

When any of the above interrupts are enabled and generated, the virtual bit, INT in the ESTAT register (Register 12-1), will be set to ‘1’. If EIE.INTIE is ‘1’, the INT pin will be driven low.

12.1.1 INT INTERRUPT REGISTERS

The registers associated with the INT interrupts are shown in Register 12-2, Register 12-3, Register 12-4 and Register 12-5.

REGISTER 12-1: ESTAT: ETHERNET STATUS REGISTER

bit 7 INT: INT Interrupt Flag bit 1 = INT interrupt is pending 0 = No INT interrupt is pending

bit 6 BUFER: Ethernet Buffer Error Status bit 1 = An Ethernet read or write has generated a buffer error (overrun or underrun) 0 = No buffer error has occurred

bit 5 Reserved: Read as ‘0’

bit 4 LATECOL: Late Collision Error bit 1 = A collision occurred after 64 bytes had been transmitted 0 = No collisions after 64 bytes have occurred

bit 3 Unimplemented: Read as ‘0’

bit 2 RXBUSY: Receive Busy bit 1 = Receive logic is receiving a data packet 0 = Receive logic is Idle

bit 1 TXABRT: Transmit Abort Error bit 1 = The transmit request was aborted 0 = No transmit abort error

bit 0 CLKRDY: Clock Ready bit(1) 1 = OST has expired; PHY is ready 0 = OST is still counting; PHY is not ready

Note 1: CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets.

REGISTER 12-2: EIE: ETHERNET INTERRUPT ENABLE REGISTER

Legend:

• R = Readable bit
• W = Writable bit
• U = Unimplemented bit, read as ‘0’
• -n = Value at POR
• ‘1’ = Bit is set
• ‘0’ = Bit is cleared
• x = Bit is unknown
• r = Reserved bit

bit 7
INTIE: Global INT Interrupt Enable bit
1 = Allow interrupt events to drive the INT pin
0 = Disable all INT pin activity (pin is continuously driven high)

bit 6
PKTIE: Receive Packet Pending Interrupt Enable bit
1 = Enable receive packet pending interrupt
0 = Disable receive packet pending interrupt

bit 5
DMAIE: DMA Interrupt Enable bit
1 = Enable DMA interrupt
0 = Disable DMA interrupt

bit 4
LINKIE: Link Status Change Interrupt Enable bit
1 = Enable link change interrupt from the PHY
0 = Disable link change interrupt

bit 3
TXIE: Transmit Enable bit
1 = Enable transmit interrupt
0 = Disable transmit interrupt

bit 2
Reserved: Maintain as ‘0’

bit 1
TXERIE: Transmit Error Interrupt Enable bit
1 = Enable transmit error interrupt
0 = Disable transmit error interrupt

bit 0
RXERIE: Receive Error Interrupt Enable bit
1 = Enable receive error interrupt
0 = Disable receive error interrupt

REGISTER 12-3: EIR: ETHERNET INTERRUPT REQUEST (FLAG) REGISTER

Legend:

• R = Readable bit
• C = Clearable bit
• U = Unimplemented bit, read as ‘0’
• -n = Value at POR
• ‘1’ = Bit is set
• ‘0’ = Bit is cleared
• x = Bit is unknown
• r = Reserved bit

bit 7
Unimplemented: Read as ‘0’

bit 6
PKTIF: Receive Packet Pending Interrupt Flag bit
1 = Receive buffer contains one or more unprocessed packets; cleared when PKTDEC is set
0 = Receive buffer is empty

bit 5
DMAIF: DMA Interrupt Flag bit
1 = DMA copy or checksum calculation has completed
0 = No DMA interrupt is pending

bit 4
LINKIF: Link Change Interrupt Flag bit
1 = PHY reports that the link status has changed; read PHIR register to clear
0 = Link status has not changed

bit 3
TXIF: Transmit Interrupt Flag bit
1 = Transmit request has ended
0 = No transmit interrupt is pending

bit 2
Reserved: Maintain as ‘0’

bit 1
TXERIF: Transmit Error Interrupt Flag bit
1 = A transmit error has occurred
0 = No transmit error has occurred

bit 0
RXERIF: Receive Error Interrupt Flag bit
1 = A packet was aborted because there is insufficient buffer space or the packet count is 255
0 = No receive error interrupt is pending

ENC28J60

REGISTER 12-4: PHIE: PHY INTERRUPT ENABLE REGISTER

Legend:

r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 15-6 Reserved: Write as ‘0’, ignore on read
bit 5 Reserved: Maintain as ‘0’
bit 4 PLNKIE: PHY Link Change Interrupt Enable bit
1 = PHY link change interrupt is enabled
0 = PHY link change interrupt is disabled
bit 3-2 Reserved: Write as ‘0’, ignore on read
bit 1 PGEIE: PHY Global Interrupt Enable bit
1 = PHY interrupts are enabled
0 = PHY interrupts are disabled
bit 0 Reserved: Maintain as ‘0’

REGISTER 12-5: PHIR: PHY INTERRUPT REQUEST (FLAG) REGISTER

Legend:

r = Reserved bit
R = Readable bit
SC = Self-Clearing bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 15-6 Reserved: Do not modify
bit 5 Reserved: Read as ‘0’
bit 4 PLNKIF: PHY Link Change Interrupt Flag bit
1 = PHY link status has changed since PHIR was last read; resets to ‘0’ when read
0 = PHY link status has not changed since PHIR was last read
bit 3 Reserved: Read as ‘0’
bit 2 PGIF: PHY Global Interrupt Flag bit
1 = One or more enabled PHY interrupts have occurred since PHIR was last read; resets to ‘0’ when read
0 = No PHY interrupts have occurred
bit 1 Reserved: Do not modify
bit 0 Reserved: Read as ‘0’

© 2006-2012 Microchip Technology Inc. DS39662E-page 67

12.1.2 RECEIVE ERROR INTERRUPT FLAG (RXERIF)

The Receive Error Interrupt Flag (RXERIF) is used to indicate a receive buffer overflow condition. Alternately, this interrupt may indicate that too many packets are in the receive buffer and more cannot be stored without overflowing the EPKTCNT register.

When a packet is being received and the receive buffer runs completely out of space, or EPKTCNT is 255 and cannot be incremented, the packet being received will be aborted (permanently lost) and the EIR.RXERIF bit will be set to '1'. Once set, RXERIF can only be cleared by the host controller or by a Reset condition. If the receive error interrupt and INT interrupt are enabled (EIE.RXERIE = 1 and EIE.INTIE = 1), an interrupt is generated by driving the \overlineINT pin low. If the receive error interrupt is not enabled (EIE.RXERIE = 0 or EIE.INTIE = 0), the host controller may poll the ENC28J60 for the RXERIF and take appropriate action.

Normally, upon the receive error condition, the host controller would process any packets pending from the receive buffer and then make additional room for future packets by advancing the ERXRDPT registers (low byte first) and decrementing the EPKTCNT register. See Section 7.2.4 "Freeing Receive Buffer Space" for more information on processing packets. Once processed, the host controller should use the BFC command to clear the EIR.RXERIF bit.

12.1.3 TRANSMIT ERROR INTERRUPT FLAG (TXERIF)

The Transmit Error Interrupt Flag (TXERIF) is used to indicate that a transmit abort has occurred. An abort can occur because of any of the following:

1. Excessive collisions occurred as defined by the Retransmission Maximum (RETMAX) bits in the MACLCON1 register.
2. A late collision occurred as defined by the Collision Window (COLWIN) bits in the MACLCON2 register.
3. A collision after transmitting 64 bytes occurred (ESTAT.LATECOL set).
4. The transmission was unable to gain an opportunity to transmit the packet because the medium was constantly occupied for too long. The deferral limit (2.4287 ms) was reached and the MAON4.DEFER bit was clear.
5. An attempt to transmit a packet larger than the maximum frame length defined by the MAMXFL registers was made without setting the MAON3.HFRMEN bit or per packet POVERRIDE and PHUGEN bits.

Upon any of these conditions, the EIR.TXERIF flag is set to '1'. Once set, it can only be cleared by the host controller or by a Reset condition. If the transmit error interrupt is enabled (EIE.TXERIE = 1 and EIE.INTIE = 1), an interrupt is generated by driving the \overlineINT pin low until the interrupt flag or interrupt enable is cleared. If the transmit error interrupt is not enabled (EIE.TXERIE = 0 or EIE.INTIE = 0), the host controller may poll the ENC28J60 for the TXERIF and take appropriate action. Once the interrupt is processed, the host controller should use the BFC command to clear the EIR.TXERIF bit.

After a transmit abort, the TXRTS bit will be cleared, the ESTAT.TXABRT bit will be set and the transmit status vector will be written at ETXND + 1. The MAC will not automatically attempt to retransmit the packet. The host controller may wish to read the transmit status vector and LATECOL bit to determine the cause of the abort. After determining the problem and solution, the host controller should clear the LATECOL (if set) and TXABRT bits so that future aborts can be detected accurately.

In Full-Duplex mode, Condition 5 is the only one that should cause this interrupt. Collisions and other problems related to sharing the network are not possible on full-duplex networks. The conditions which cause the transmit error interrupt meet the requirements of the transmit interrupt. As a result, when this interrupt occurs, TXIF will also be simultaneously set.

12.1.4 TRANSMIT INTERRUPT FLAG (TXIF)

The Transmit Interrupt Flag (TXIF) is used to indicate that the requested packet transmission has ended (ECON1.TXRTS has transitioned from '1' to '0'). Upon transmission completion, abort or transmission cancellation by the host controller, the EIR.TXIF flag will be set to '1'. If the host controller did not clear the TXRTS bit and the ESTAT.TXABRT bit is not set, then the packet was successfully transmitted. Once TXIF is set, it can only be cleared by the host controller or by a Reset condition. If the transmit interrupt is enabled (EIE.TXIE = 1 and EIE.INTIE = 1), an interrupt is generated by driving the \overlineINT pin low. If the transmit interrupt is not enabled (EIE.TXIE = 0 or EIE.INTIE = 0), the host controller may poll the ENC28J60 for the TXIF bit and take appropriate action. Once processed, the host controller should use the BFC command to clear the EIR.TXIF bit.

12.1.5 LINK CHANGE INTERRUPT FLAG (LINKIF)

The LINKIF indicates that the link status has changed. The actual current link status can be obtained from the PHSTAT1.LLSTAT or PHSTAT2.LSTAT (see Register 3-5 and Register 3-6). Unlike other interrupt sources, the link status change interrupt is created in the integrated PHY module; additional steps must be taken to enable it.

By Reset default, LINKIF is never set for any reason. To receive it, the host controller must set the PHIE.PLNKIE and PGEIE bits. After setting the two PHY interrupt enable bits, the LINKIF bit will then shadow the contents of the PHIR.PGIF bit. The PHY only supports one interrupt, so the PGIF bit will always be the same as the PHIR.PLNKIF bit (when both PHY enable bits are set).

Once LINKIF is set, it can only be cleared by the host controller or by a Reset. If the link change interrupt is enabled (EIE.LINKIE = 1, EIE.INTIE = 1, PHIE.PLNKIE = 1 and PHIE.PGEIE = 1), an interrupt will be generated by driving the \overlineINT pin low. If the link change interrupt is not enabled (EIE.LINKIE = 0, EIE.INTIE = 0, PHIE.PLNKIE = 0 or PHIE.PGEIE = 0), the host controller may poll the ENC28J60 for the PHIR.PLNKIF bit and take appropriate action.

The LINKIF bit is read-only. Because reading from PHY registers requires non-negligible time, the host controller may instead set PHIE.PLNKIE and PHIE.PGEIE and then poll the EIR.LINKIF bit. Performing an MII read on the PHIR register will clear the LINKIF, PGIF and PLNKIF bits automatically and allow for future link status change interrupts. See Section 3.3 “PHY Registers” for information on accessing the PHY registers.

12.1.6 DMA INTERRUPT FLAG (DMAIF)

The DMA interrupt indicates that the DMA module has completed its memory copy or checksum calculation (ECON1.DMAST has transitioned from ‘1’ to ‘0’). Additionally, this interrupt will be caused if the host controller cancels a DMA operation by manually clearing the DMAST bit. Once set, DMAIF can only be cleared by the host controller or by a Reset condition. If the DMA interrupt is enabled (EIE.DMAIE = 1 and EIE.INTIE = 1), an interrupt is generated by driving the \overlineINT pin low. If the DMA interrupt is not enabled (EIE.DMAIE = 0 or EIE.INTIE = 0), the host controller may poll the ENC28J60 for the DMAIF and take appropriate action. Once processed, the host controller should use the BFC command to clear the EIR.DMAIF bit.

12.1.7 RECEIVE PACKET PENDING INTERRUPT FLAG (PKTIF)

The Receive Packet Pending Interrupt Flag (PKTIF) is used to indicate the presence of one or more data packets in the receive buffer and to provide a notification means for the arrival of new packets. When the receive buffer has at least one packet in it, EIR.PKTIF will be set. In other words, this interrupt flag will be set anytime the Ethernet Packet Count register (EPKTCNT) is non-zero. If the receive packet pending interrupt is enabled (EIE.PKTIE = 1 and EIE.INTIE = 1), an interrupt will be generated by driving the \overlineINT pin low whenever a new packet is successfully received and written into the receive buffer. If the receive packet pending interrupt is not enabled (EIE.PKTIE = 0 or EIE.INTIE = 0), the host controller will not be notified when new packets arrive. However, it may poll the PKTIF bit and take appropriate action.

The PKTIF bit can only be cleared by the host controller or by a Reset condition. In order to clear PKTIF, the EPKTCNT register must be decremented to ‘0’. See Section 7.2 “Receiving Packets” for more information about clearing the EPKTCNT register. If the last data packet in the receive buffer is processed, EPKTCNT will become zero and the PKTIF bit will automatically be cleared.

12.2 Wake-On-LAN/Remote Wake-up

Wake-On-LAN or Remote Wake-up is useful in conserving system power. The host controller and other subsystems can be put in Low-Power mode and be woken up by the ENC28J60 when a wake-up packet is received from a remote station. The ENC28J60 must not be in Power-Save mode and the transmit and receive modules must be enabled in order to receive a wake-up packet. The ENC28J60 wakes up the host controller via the \overlineINT signal when the Interrupt Mask registers are properly configured. The receive filter can also be set up to only receive a specific wake-up packet (see Register 8-1 for available options). Section 12.2.1 "Setup Steps for Waking Up on a Magic Packet" shows the steps necessary in configuring the ENC28J60 to send an interrupt signal to the host controller upon the reception of a Magic Packet.

12.2.1 SETUP STEPS FOR WAKING UP ON A MAGIC PACKET

1. Set ERXFCON.CRCEN and ERXFCON.MPEN.
2. Service all pending packets.
3. Set EIE.PKTIE and EIE.INTIE.
4. Set up the host controller to wake-up on an external interrupt \overlineINT signal.
5. Put the host controller and other subsystems to Sleep to save power.

Once a Magic Packet is received, the EPKTCNT is incremented to '1', which causes the EIR.PKTIF bit to set. In turn, the ESTAT.INT bit is set and the \overlineINT signal is driven low, causing the host to wake-up.

13.0 DIRECT MEMORY ACCESS CONTROLLER

The ENC28J60 incorporates a dual purpose DMA controller which can be used to copy data between locations within the 8-Kbyte memory buffer. It can also be used to calculate a 16-bit checksum which is compatible with various industry standard protocols, including TCP and IP.

When a DMA operation begins, the EDMAST register pair is copied into an Internal Source Pointer. The DMA will execute on one byte at a time and then increment the Internal Source Pointer. However, if a byte is processed and the Internal Source Pointer is equal to the Receive Buffer End Pointer, ERXND, the Source Pointer will not be incremented. Instead, the Internal Source Pointer will be loaded with the Receive Buffer Start Pointer, ERXST. In this way, the DMA will follow the circular FIFO structure of the receive buffer and received packets can be processed using one operation. The DMA operation will end when the Internal Source Pointer matches the EDMAND Pointer.

While any DMA operation is in progress, the DMA Pointers and the ECON1.CSUMEN bit should not be modified. The DMA operation can be canceled at any time by clearing the ECON1.DMAST bit. No registers will change; however, some memory bytes may already have been copied if a DMA copy was in progress.

Note 1: If the EDMAND Pointer cannot be reached because of the receive buffer wrapping behavior, the DMA operation will never end.

2: By design, the DMA module cannot be used to copy only one byte (EDMAST = EDMAND). An attempt to do so will overwrite all memory in the buffer and may never end.

13.1 Copying Memory

To copy memory within the buffer:

1. Appropriately program the EDMAST, EDMAND and EDMADST register pairs. The EDMAST registers should point to the first byte to copy from, the EDMAND registers should point to the last byte to copy and the EDMADST registers should point to the first byte in the destination range. The destination range will always be linear, never wrapping at any values except from 8191 to 0 (the 8-Kbyte memory boundary). Extreme care should be taken when programming the Start and End Pointers to prevent a never ending DMA operation which would overwrite the entire 8-Kbyte buffer.
2. If an interrupt at the end of the copy process is desired, set EIE.DMAIE and EIE.INTIE and clear EIR.DMAIF.
3. Verify that ECON1.CSUMEN is clear.
4. Start the DMA copy by setting ECON1.DMAST.

If a transmit operation is in progress (TXRTS set) while the DMAST bit is set, the ENC28J60 will wait until the transmit operation is complete before attempting to do the DMA copy. This possible delay is required because the DMA and transmission engine share the same memory access port.

When the copy is complete, the DMA hardware will clear the DMAST bit, set the DMAIF bit and generate an interrupt (if enabled). The pointers and the EDMACS registers will not be modified.

After the DMA module has been initialized and has begun its copy, two main clock cycles will be required for each byte copied. As a result, if a maximum size 1518-byte packet was copied, the DMA module would require slightly more than 121.44 µs to complete. The time required to copy a minimum size packet of 64 bytes would be dominated by the time required to configure the DMA.

13.2 Checksum Calculations

The checksum calculation logic treats the source data as a series of 16-bit big-endian integers. If the source range contains an odd number of bytes, a padding byte of 00h is effectively added to the end of the series for purposes of calculating the checksum. The calculated checksum is the 16-bit one's complement of the one's complement sum of all 16-bit integers. For example, if the bytes included in the checksum were {89h, ABh, CDh}, the checksum would begin by computing 89ABh + CD00h. A carry out of the 16th bit would occur in the example, so in 16-bit one's complement arithmetic, it would be added back to the first bit. The resulting value of 56ACH would finally be complemented to achieve a checksum of A953h.

To calculate a checksum:

1. Program the EDMAST and EDMAND register pairs to point to the first and last bytes of buffer data to be included in the checksum. Care should be taken when programming these pointers to prevent a never ending checksum calculation due to receive buffer wrapping.
2. To generate an optional interrupt when the checksum calculation is done, clear EIR.DMAIF, set EIE.DMAIE and set EIE.INTIE.
3. Start the calculation by setting ECON1.CSUMEN and ECON1.DMAST.

When the checksum is finished being calculated, the hardware will clear the DMAST bit, set the DMAIF bit and an interrupt will be generated if enabled. The DMA Pointers will not be modified and no memory will be written to. The EDMACSH and EDMACSL registers will contain the calculated checksum. The host controller may write this value into a packet, compare this value with a received checksum, or use it for other purposes.

Various protocols, such as TCP and IP, have a checksum field inside a range of data which the checksum covers. If such a packet is received and the host controller needs to validate the checksum, it can do the following:

1. Read the checksum from the packet and save it to a temporary location
2. Write zeros to the checksum field.
3. Calculate a new checksum using the DMA controller.
4. Compare the results with the saved checksum from Step 1.

Writing to the receive buffer is permitted when the write address is protected by means of the ERXRDPT Pointers. See Section 7.2 "Receiving Packets" for additional information.

The IP checksum has unique mathematical properties which may be used in some cases to reduce the processing requirements further. Writing to the receive buffer may be unnecessary in some applications.

When operating the DMA in Checksum mode, it will take one main clock cycle for every byte included in the checksum. As a result, if a checksum over 1446 bytes were performed, the DMA module would require slightly more than 57.84 \mus to complete the operation.

TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DMA CONTROLLER

Legend: r = reserved bit, — = unimplemented, read as ‘0’. Shaded cells are not used with the DMA controller.

14.0 POWER-DOWN

The ENC28J60 may be commanded to power-down via the SPI interface. When powered down, it will no longer be able to transmit and receive any packets.

To maximize power savings:

1. Turn off packet reception by clearing ECON1.RXEN.
2. Wait for any in-progress packets to finish being received by polling ESTAT.RXBUSY. This bit should be clear before proceeding.
3. Wait for any current transmissions to end by confirming ECON1.TXRTS is clear.
4. Set ECON2.VRPS (if not already set).
5. Enter Sleep by setting ECON2.PWRSV. All MAC, MII and PHY registers become inaccessible as a result. Setting PWRSV also clears ESTAT.CLKRDY automatically.

In Sleep mode, all registers and buffer memory will maintain their states. The ETH registers and buffer memory will still be accessible by the host controller. Additionally, the clock driver will continue to operate. The CLKOUT function will be unaffected (see Section 2.3 "CLKOUT Pin").

When normal operation is desired, the host controller must perform a slightly modified procedure:

1. Wake-up by clearing ECON2.PWRSV.
2. Wait at least 300 µs for the PHY to stabilize. To accomplish the delay, the host controller may poll ESTAT.CLKRDY and wait for it to become set.
3. Restore receive capability by setting ECON1.RXEN.

After leaving Sleep mode, there is a delay of many milliseconds before a new link is established (assuming an appropriate link partner is present). The host controller may wish to wait until the link is established before attempting to transmit any packets. The link status can be determined by polling the PHSTAT2.LSTAT bit. Alternatively, the link change interrupt may be used if it is enabled. See Section 12.1.5 "Link Change Interrupt Flag (LINKIF)" for additional details.

TABLE 14-1: SUMMARY OF REGISTERS USED WITH POWER-DOWN

Legend: — = unimplemented, read as ‘0’, r = reserved bit. Shaded cells are not used for power-down.

Note 1: CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets.

NOTES:

.

15.0 BUILT-IN SELF-TEST CONTROLLER

The ENC28J60 features a Built-in Self-Test (BIST) module which is designed to confirm proper operation of each bit in the 8-Kbyte memory buffer. Although it is primarily useful for testing during manufacturing, it remains present and available for diagnostic purposes by the user. The controller writes to all locations in the buffer memory and requires several pieces of hardware shared by normal Ethernet operations. Thus, the BIST should only be used on Reset or after necessary hardware is freed. When the BIST is used, the ECON1 register’s DMAST, RXEN and TXRTS bits should all be clear.

The BIST controller is operated through four registers:

• EBSTCON register (control and status register)
• EBSTSD register (fill seed/initial shift value)
• EBSTCSH and EBSTCSL registers (high and low bytes of generated checksum)

The EBSTCON register (Register 15-1) controls the module’s overall operation, selecting the Testing modes and starting the self-test process. The bit pattern for memory tests is provided by the EBSTSD seed register; its content is either used directly, or as the seed for a pseudo-random number generator, depending on the Test mode.

REGISTER 15-1: EBSTCON: ETHERNET SELF-TEST CONTROL REGISTER

bit 7-5 PSV<2:0>: Pattern Shift Value bits When TMSEL<1:0> = 10: The bits in EBSTSD will shift left by this amount after writing to each memory location. When TMSEL<1:0> = 00, 01 or 11: This value is ignored.

bit 4 PSEL: Port Select bit 1 = DMA and BIST modules will swap ports when accessing the memory 0 = Normal configuration

bit 3-2 TMSEL<1:0>: Test Mode Select bits 11 = Reserved 10 = Pattern shift fill 01 = Address fill 00 = Random data fill

bit 1 TME: Test Mode Enable bit 1 = Enable Test mode 0 = Disable Test mode

bit 0 BISTST: Built-in Self-Test Start/Busy bit 1 = Test in progress; cleared automatically when test is done 0 = No test running

15.1 Using the BIST

When the BIST controller is started, it will fill the entire buffer with the data generated for the current test configuration and it will also calculate a checksum of the data as it is written. When the BIST is complete, the EBSTCS registers will be updated with the checksum. The host controller will be able to determine if the test passed or failed by using the DMA module to calculate a checksum of all memory. The resulting checksum generated by the DMA should match the BIST checksum. If after any properly executed test, the checksums differ, a hardware Fault may be suspected.

The BIST controller supports 3 different operations:

• Random Data Fill
• Address Fill
• Pattern Shift Fill

The ports through which the BIST and DMA modules access the dual port SRAM can be swapped for each of the four Test modes to ensure proper read/write capability from both ports.

To use the BIST:

1. Program the EDMAST register pair to 0000h.
2. Program EDMAND and ERXND register pairs to 1FFFh.
3. Configure the DMA for checksum generation by setting CSUMEN in ECON1.
4. Write the seed/initial shift value byte to the EBSTSD register (this is not necessary if Address Fill mode is used).
5. Enable Test mode, select the desired test, select the desired port configuration for the test.
6. Start the BIST by setting EBSTCON.BISTST.
7. Start the DMA checksum by setting DMAST in ECON1. The DMA controller will read the memory at the same rate the BIST controller will write to it, so the DMA can be started any time after the BIST is started.
8. Wait for the DMA to complete by polling the DMAST bit or receiving the DMA interrupt (if enabled).
9. Compare the EDMACS registers with the EBSTCS registers.

To ensure full testing, the test should be redone with the Port Select bit, PSEL, altered. When not using Address Fill mode, additional tests may be done with different seed values to gain greater confidence that the memory is working as expected.

At any time during a test, the test can be canceled by clearing the BISTST, DMAST and TME bits. While the BIST is filling memory, the EBSTSD register should not be accessed, nor should any configuration changes occur. When the BIST completes its memory fill and checksum generation, the BISTST bit will automatically be cleared.

The BIST module requires one main clock cycle for each byte that it writes into the RAM. The DMA module’s checksum implementation requires the same time but it can be started immediately after the BIST is started. As a result, the minimum time required to do one test pass is slightly greater than 327.68 μs.

15.2 Random Data Fill Mode

In Random Data Fill mode, the BIST controller will write pseudo-random data into the buffer. The random data is generated by a Linear Feedback Shift Register (LFSR) implementation. The random number generator is seeded by the initial contents of the EBSTSD register and the register will have new contents when the BIST is finished.

Because of the LFSR implementation, an initial seed of zero will generate a continuous pattern of zeros. As a result, a non-zero seed value will likely perform a more extensive memory test. Selecting the same seed for two separate trials will allow a repeat of the same test.

15.3 Address Fill Mode

In Address Fill mode, the BIST controller will write the low byte of each memory address into the associated buffer location. As an example, after the BIST is operated, the location 0000h should have 00h in it, location 0001h should have 01h in it, location 0E2Ah should have 2Ah in it and so on. With this fixed memory pattern, the BIST and DMA modules should always generate a checksum of F807h. The host controller may use Address Fill mode to confirm that the BIST and DMA modules themselves are both operating as intended.

15.4 Pattern Shift Fill Mode

In Pattern Shift Fill mode, the BIST controller writes the value of EBSTSD into memory location 0000h. Before writing to location 0001h, it shifts the contents of EBSTSD to the left by the value specified by the PSV2:PSV0 bits in EBSTCON. Bits that leave the most significant end of EBSTSD are wrapped around to the least significant side. This shift is repeated for each new address. As a result of shifting the data, a checkerboard pattern can be written into the buffer memory to confirm that adjacent memory elements do not affect each other when accessed.

TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE SELF-TEST CONTROLLER

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used.

NOTES:

DS39662E-page 78 . © 2006-2012 Microchip Technology Inc.

16.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

• Storage temperature ........ -65°C to +150°C
• Ambient temperature under bias ........ -40°C to +85°C (Industrial)
• ........ 0°C to +70°C (Commercial)
• Voltage on VDD, VDDOSC, VDDPLL, VDDRX and VDDTX, with respect to VSS ........ -0.3V to 3.6V
• Voltage on \overlineRESET, \overlineCS, SCK and SI, with respect to VSS ........ -0.3V to 6.0V
• Voltage on CLKOUT, SO, OSC1, OSC2, LEDA and LEDB, with respect to VSS ........ -0.3V to VDD + 0.3V
• Voltage on TPIN+/- and TPOUT+/- with respect to VSS ........ -0.3V to 5.0V
• VCAP with respect to VSS (Note 1) ........ -0.3V to 2.75V
• ESD protection on all pins ........ 2 kV
• Current sourced or sunk by LEDA, LEDB ........ 12 mA
• Current sourced or sunk by CLKOUT ........ 8 mA
• Current sourced or sunk by \overlineINT and SO ........ 4 mA

Note 1: VCAP is not designed to supply an external load. No external voltage should be applied to this pin.

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

16.1 DC Characteristics: ENC28J60 (Industrial and Commercial)

Note 1: Negative current is defined as current sourced by the pin.

DS39662E-page 80 © 2006-2012 Microchip Technology Inc.

TABLE 16-1: AC CHARACTERISTICS: ENC28J60 (INDUSTRIAL AND COMMERCIAL)

| AC CHARACTERISTICS | Standard Operating Conditions-40°C ≤ TA ≤ +85°C, 3.10V ≤ VDD ≤ 3.60V (Industrial)0°C ≤ TA ≤ +70°C, 3.10V ≤ VDD ≤ 3.60V (Commercial) |

TABLE 16-2: OSCILLATOR TIMING CHARACTERISTICS

TABLE 16-3: RESET AC CHARACTERISTICS

TABLE 16-4: CLKOUT PIN AC CHARACTERISTICS

Note 1: CLKOUT prescaler is set to divide by one.

TABLE 16-5: REQUIREMENTS FOR EXTERNAL MAGNETICS

FIGURE 16-1: SPI INPUT TIMING

FIGURE 16-2: SPI OUTPUT TIMING

TABLE 16-6: SPI INTERFACE AC CHARACTERISTICS

DS39662E-page 82 © 2006-2012 Microchip Technology Inc.

17.0 PACKAGING INFORMATION

17.1 Package Marking Information

28-Lead SPDIP

Example

28-Lead SOIC

Example

28-Lead SSOP

Example

28-Lead QFN

Example

Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn)

• This package is Pb-free. The Pb-free JEDEC designator (e3) can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

17.2 Package Details

The following sections give the technical details of the packages.

28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e .100 BSC Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .050 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-070B

28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Microchip Technology Drawing C04-052C Sheet 1 of 2

28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
   BSC: Basic Dimension. Theoretically exact value shown without tolerances.
   REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing C04-052C Sheet 2 of 2

DS39662E-page 86 © 2006-2012 Microchip Technology Inc.

28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

RECOMMENDED LAND PATTERN

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M
   BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2052A

28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-073B

28-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

RECOMMENDED LAND PATTERN

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M
   BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2073A

28-Lead Plastic Quad Flat, No Lead Package (ML) - 6x6 mm Body [QFN] With 0.55 mm Terminal Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Microchip Technology Drawing C04-105C Sheet 1 of 2

28-Lead Plastic Quad Flat, No Lead Package (ML) - 6x6 mm Body [QFN]

With 0.55 mm Terminal Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M.
   BSC: Basic Dimension. Theoretically exact value shown without tolerances.
   REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-105C Sheet 2 of 2

28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN] with 0.55 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

RECOMMENDED LAND PATTERN

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M
   BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2105A

DS39662E-page 92 © 2006-2012 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision A (January 2006) Original data sheet for the ENC28J60.

Revision B (July 2006) Minor edits and format changes throughout the document.

Revision C (January 2008) Added one line to the “Ethernet Controller Features” section and added omitted revision history. Minor edits to text throughout document.

Revision D (July 2012) Updated package drawings in Section 17.0, Packaging Information and updated marking examples in the “Product Identification System” section. Minor edits and format changes throughout the document.

Revision E (November 2012) Removed references to Commercial temperatures; specifically in Section 17.0 “Packaging Information” and the Product Identification System section.

NOTES:

.

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• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
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To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.

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Users of Microchip products can receive assistance through several channels:

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Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.

Technical support is available through the web site at: http://microchip.com/support

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

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DS39662E-page 96 . © 2006-2012 Microchip Technology Inc.

INDEX

A

AC Characteristics

• CLKOUT Pin ........ 81
• Industrial and Commercial ........ 81
• Reset ........ 81
• SPI Interface (table) ........ 82

B

BIST

• Address Fill Mode ........ 76
• Associated Registers ........ 77
• EBSTCS registers ........ 76
• EBSTSD Register ........ 76
• Pattern Shift Fill Mode ........ 76
• Random Data Fill Mode ........ 76
• Usage ........ 76

Block Diagrams

• Crystal Oscillator Operation ........ 5

• ENC28J60 Architecture ........ 3

• Ethernet Buffer Organization ........ 18

• Ethernet Packet Format ........ 31

• Ethernet Termination and External Connections 7

• External Clock Source ........ 5

• I/O Level Shifting Using 3-State Buffers ........ 8

• I/O Level Shifting Using AND Gates ........ 8

• Interrupt Logic ........ 63

• LEDB Polarity and Reset Configuration ........ 8

• Magic Packet Format ........ 52

• Memory Organization ........ 11

• On-Chip Reset Circuit ........ 59

• Pattern Match Filter Format ........ 51

• Typical ENC28J60 Based Interface ........ 4

• Built-in Self-Test Controller (BIST) ........ 75

C

• Checksum Calculations ........ 72
• CLKOUT Pin ........ 6
• Control Register Summary ........ 13–14
• Control Registers ........ 12
• Map ........ 12
• Customer Change Notification Service ........ 95
• Customer Notification Service ........ 95
• Customer Support ........ 95

D

DC Characteristics

• Industrial and Commercial ........ 80

• DMA Controller ........ 71

• Associated Registers ........ 72

• Checksum Calculations ........ 72

• Copying Memory ........ 71

Duplex Mode

• Configuration and Negotiation ........ 53

E

• Electrical Characteristics ........ 79

• Absolute Maximum Ratings ........ 79

• Oscillator Timing ........ 81

• Requirements for External Magnetics ........ 81

• EREVID Register ........ 22

• Errata ........ 2

Ethernet

• Packet Format ........ 31

• CRC Field ........ 32

• Data Field ........ 32

• Destination Address ........ 32

• Padding Field ........ 32

• Preamble/Start-of-Frame Delimiter ........ 31

• Source Address ........ 32

• Type/Length Field ........ 32

• Ethernet Buffer ........ 17 DMA Controller

• Access ........ 17

• Reading and Writing ........ 17

• Receive ........ 17

• Transmit ........ 17

Ethernet Module

• Transmitting and Receiving Data

  • Receive Packet Layout ........ 43
  • Transmit Packet Layout ........ 40

• Ethernet Overview ........ 31

F

• Flow Control ........ 55
• Associated Registers ........ 57
• Full-Duplex Mode ........ 55
• Half-Duplex Mode ........ 55
• Sample Full-Duplex Network (Diagram) ........ 55

Flowcharts

• Receive Filters Using AND Logic ........ 50
• Receive Filters Using OR Logic ........ 49

Full-Duplex Mode

• Operation ........ 53

H

Half-Duplex Mode

• Operation ........ 53

I

• I/O Level Shifting ........ 8

• Initialization ........ 33

• MAC Settings ........ 34

• PHY Settings ........ 37

• Receive Buffer ........ 33

• Receive Filters ........ 33

• Transmit Buffer ........ 33

• Waiting for OST ........ 33

• Internet Address ........ 95

• Interrupts ........ 63

• DMA Flag (DMAIF) ........ 69

• INT Enable (INTIE) ........ 64

• Link Change Flag (LINKIF) ........ 69

• Receive Error Flag (RXERIF) ........ 68

• Receive Packet Pending Flag (PKTIF) ........ 69

• Transmit Error Flag (TXERIF) ........ 68

• Transmit Interrupt Flag (TXIF) ........ 68

L

• LED Configuration ........ 8

M

• Magnetics and External Components ........ 7
• Memory Organization ........ 11
• Microchip Internet Web Site ........ 95

O

• Oscillator ........ 5
• Start-up Timer (OST) ........ 5

P

• Package Types ........ 1
• Packaging Information ........ 83
• Details ........ 84
• Marking ........ 83
• Per Packet Control Byte Format ........ 39
• PHID Registers ........ 22
• PHSTAT Registers ........ 22
• PHY Register Summary ........ 20
• PHY Registers ........ 19
• Reading ........ 19
• Scanning ........ 19
• Writing ........ 19
• Pin Diagrams ........ 1
• Pinout I/O Descriptions ........ 4
• Power-Down ........ 73
• Associated Registers ........ 73
• Power-on Reset (POR) ........ 60

R

• Read Control Register (RCR) ........ 27
• Reader Response ........ 96
• Receive Filters ........ 47
• Broadcast ........ 52
• Hash Table ........ 52
• Magic Packet ........ 52
• Multicast ........ 52
• Pattern Match Filter ........ 51
• Unicast Filter ........ 51
• Receiving Packets ........ 43
• Associated Registers ........ 46
• Calculating Buffer Free Space ........ 45
• Calculating Free Receive Buffer Space ........ 45
• Calculating Random Access Address ........ 44
• Enabling Reception ........ 43
• Freeing Buffer Space ........ 45
• Layout ........ 43
• Reading ........ 44
• Status Vectors ........ 44 Registers
• EBSTCON (Ethernet Self-Test Control) ........ 75
• ECOCON (Clock Output Control) ........ 6
• ECON1 (Ethernet Control 1) ........ 15
• ECON2 (Ethernet Control 2) ........ 16
• EFLOCON (Ethernet Flow Control) ........ 56
• EIE (Ethernet Interrupt Enable) ........ 65
• EIR (Ethernet Interrupt Request, Flag) ........ 66
• ERXFCON (Ethernet Receive Filter Control) ........ 48
• ESTAT (Ethernet Status) ........ 64
• MABBIPG (MAC Back-to-Back Inter-Packet Gap) ........ 36
• MACON1 (MAC Control 1) ........ 34
• MACON3 (MAC Control 3) ........ 35
• MACON4 (MAC Control 4) ........ 36
• MICMD (MII Command) ........ 21
• MISTAT (MII Status) ........ 21
• PHCON1 (PHY Control 1) ........ 61
• PHCON2 (PHY Control 2) ........ 37
• PHID (PHY Device ID) ........ 22
• PHIE (PHY Interrupt Enable) ........ 67
• PHIR (PHY Interrupt Request, Flag) ........ 67
• PHLCON (PHY Module LED Control) ........ 9
• PHSTAT1 (Physical Layer Status 1) ........ 23
• PHSTAT2 (Physical Layer Status 2) ........ 24
• Resets ........ 59
• MAC, PHY Subsystem ........ 61
• Power-on Reset ........ 60
• Receive Only ........ 60
• System ........ 60
• Transmit Only ........ 60
• Revision History ........ 93

S Serial Peripheral Interface. See SPI. SPI

• Bit Field Clear Command ........ 29
• Bit Field Set Command ........ 29
• Instruction Set ........ 26
• Overview ........ 25 Read Buffer
• Memory Command ........ 28
• Read Control Register Command ........ 27
• System Reset Command ........ 30 Write Buffer
• Memory Command ........ 29
• Write Control Register Command ........ 28

T

• Termination Requirement ........ 7 Timing Diagrams
• CLKOUT Transition ........ 6 Read Control Register Command
• (ETH Registers) ........ 27 Read Control Register Command
• (MAC/MII Registers) ........ 27
• SPI Input ........ 25, 82
• SPI Output ........ 25, 82
• System Reset Command Sequence ........ 30
• Write Buffer Memory Command Sequence ........ 29
• Write Control Register Command Sequence ........ 28
• Transmitting Packets ........ 39
• Associated Registers ........ 42
• Status Vectors ........ 41

W

• WWW Address ........ 95
• WWW, On-Line Support ........ 2

DS39662E-page 98 © 2006-2012 Microchip Technology Inc.

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device

• ENC28J60: Ethernet Controller w/SPI Interface
• ENC28J60T: Ethernet Controller w/SPI Interface (Tape and Reel)

Temperature Range

• I = -40°C to +85°C (Industrial) (SPDIP, SOIC, SSOP and QFN packages)
• (Blank) = 0°C to +70°C (Commercial) (SSOP packages only)

Package

• SP = SPDIP (Skinny Plastic DIP)
• SO = SOIC (Plastic Small Outline)
• SS = SSOP (Plastic Shrink Small Outline)
• ML = QFN (Quad Flat No Lead)

Examples:

a) ENC28J60-I/SP: Industrial temperature, SPDIP package. b) ENC28J60-I/SO: Industrial temperature, SOIC package. c) ENC28J60T-I/SO: Tape and Reel, Industrial temperature, SOIC package. d) ENC28J60/SS: Commercial temperature, SSOP package. e) ENC28J60T-I/SS: Tape and Reel, Industrial temperature, SSOP package. f) ENC28J60-I/ML: Industrial temperature, QFN package.

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC$^{32}$ logo, rFPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2006-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-62076-686-6

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China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118

China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256

China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130

China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123

India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632

India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513

Japan - Osaka
Tel: 81-66-152-7160
Fax: 81-66-152-9310

Japan - Yokohama
Tel: 81-45-471-6166
Fax: 81-45-471-6122

Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302

Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or 82-2-558-5934

Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859

Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068

Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069

Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850

Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955

Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305

Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102

Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350

EUROPE

Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393

Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829

France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79

Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44

Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781

Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340

Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91

UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820

10/26/12