Has anyone seen output pins cause a design to randomnly fail?
I have a very solid design that I accidently left two OBUFs with no ucf LOC contraint. depending how much i fill a v2pro device my logic will fail seemingly randmonly with these two OBUFs instantiated.
I know that the randomn locations that ISE is choosing is not colliding with anything on my board but the design fails consistenly.
Thoughts?
Matt