Hi All, I'm kinda new in the business so this question may be very rookie. Anyways, I was wondering if all synchronous designs need to be state machine based designed or the synchronous behaviour can be modelled using multiple clocked processes like always (in Verilog) blocks activated by clock to do the same thing. Thanks morpheus
Synchronous design
Feb 24, 2005
1 Replies
A synchronous design entity (module) contains one or more clocked processes (always blocks). A clocked process that updates an enumerated local variable rather than a vector or integer is sometimes called a state machine. A single clocked process can also update multiple process variables.
-- Mike Treseler
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