serial protocol specs and verification

alb · 2013-07-26T15:22:36+00:00

Hi all, I have the following specs for the physical level of a serial protocol: Isn't there a missing requirement on reset condition of the line? System clock is implicitly defined on a different section of the specs and is set at 40MHz. At the next layer there's a definition of a 'frame' as a sequence of 16 bit words preceded by a 3 bit sync pattern (111) and a header of 16 bits defining the type of the packet and the length of the packet (in words). I'm writing a test bench for it and I was wondering whether there's any recommendation you would suggest. Should I take care about randomly select the phase between the system clock and the data? Any pointer is appreciated. Cheers, Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?

Jul 26, 2013 41 Replies

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RCIngham 12 years ago

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Simulation or other experiment will indicate which of us (if either) is correct.

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edmoore 12 years ago

Xilinx Xapp224 , which describes data recovery using 4x oversampling, might be useful to the OP.

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