and,,,
If you skip up a few replies in this thread, you will see the standard that was written that created this strange requirement.
If I was paranoid, I might think that ASIC designers do stuff like this intentionally to prevent anyone from muscling in on their turf with FPGAs.
But, that would be silly.
Austin
Since it does not seem to be many pins that need this, why not implement it by allocating two FPGA pins ? Then, you CAN easily control it from the logic, with little PCB cost.
With an external resistor, and a terminate pin, you can control the load as PullUp, PullDown, or Float ?
-jg
Well, that structure is also common in Microcontrollers, so the one out of step here, is the (much smaller) FPGA sector :)
But, as per my other post, you can pretty much create this using two pins on a FPGA, and there are not many IOs where this is vital, so the system cost is small.
-jg
Hi,
The ASIC product we are designing is basically a "generic" microcontoller together with a mixed signal section. The ASIC has a very low pincount, most of which are used for power/ground/clocks.
This ASIC will be used in a number of products, each with unique GPIO requirements (thus the programmability). If you check out data sheets for microcontrollers (e.g. PIC), you can see that programmable pull configurations are very common.
I can see that for an FPGA based product, then the functionality may not be required (although I would be concerned about supporting N devices intead of 1), but we are using FPGA's as a (F/W and system) development and proving platform so we need minimal changes.
The "two pin solution" is interesting and provdes the required functionality, but I am not sure that we have the spare pins/ connectivity etc on our off the FPGA evaluation board (the expansion area will be used for our mixed signal system).
Thanks for the feedback,
Steven
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