Has anyone given any thought to rocket IO testing. I have to write some test firmware and can't find any advice of the XILINX site.
Lets assume that all my links go between FPGA's but that I don't want to have to control the transmitter and receiver as each FPGA is coupled to a different processor across a subrack.
My best option seems to be to free run the transmitter with a clock correction packet, followed by a byte sync(Comma) followed by a 1024 byte packet( each byte from an LFSR) with CRC enabled. Each receiver can then throw away the data and check that it's getting the correct number of packets/second and that none of the many error flags (in particular the CRC of course) are getting set.
In the long term it would be nice if I could control the transmitter at the same time so that I could force CRC errors and watch for them being received or turn off 8B10B for a while and plot BER against edge transitions so that getting a BER for the application becomes easier.
Any suggestions or url's greatly appreciated.