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August 4, 2003, 5:09 pm

Your design should fit going from the 9500 to the 9500xl. The 9500xl
actually has more function block fanin (36 to 54!) so I would think
that there should be no fitting issues. The only architectural
features lost are macrocell feedback and wire-anding in the AIM. The
loss of macrocell feedback should be made up for by the additional FB
inputs. The loss of wire-anding would cause your PTerm requirements to
increase. Perhaps if you were near the maximum utilization for this it
would not fit.
You may want to try contacting the Xilinx hotline. They are willing to
try fitting close designs.
Arthur
snipped-for-privacy@cygrp.com (Aare Tali) wrote in message

actually has more function block fanin (36 to 54!) so I would think
that there should be no fitting issues. The only architectural
features lost are macrocell feedback and wire-anding in the AIM. The
loss of macrocell feedback should be made up for by the additional FB
inputs. The loss of wire-anding would cause your PTerm requirements to
increase. Perhaps if you were near the maximum utilization for this it
would not fit.
You may want to try contacting the Xilinx hotline. They are willing to
try fitting close designs.
Arthur
snipped-for-privacy@cygrp.com (Aare Tali) wrote in message


Re: Design fits XC9536 but not XC9536XL
: actually has more function block fanin (36 to 54!) so I would think
: that there should be no fitting issues.
That's what I hoped, but no luck (so far).
: The loss of wire-anding would cause your PTerm requirements to
: increase. Perhaps if you were near the maximum utilization for this it
: would not fit.
I suspect that is it. The report I get from the failed XC9536XL fit is:
"Mapping a total of 36 equations into 2 function blocks......
ERROR:Cpld:935 - Cannot place signal P<3>. Consider reducing
the collapsing input limit or the product term limit to prevent
the fitter from creating high input and/or high product term
functions".
When successfully put into an XC9536 the report says:
Macrocells used: 36/36 (100%)
Product terms used: 146/180 (81%)
Registers used: 36/36 (100%)
Pins used: 34/34 (100%)
Function block inputs used: 56/72 (77%)
There are lots of signals shown as "wire-AND input".
: You may want to try contacting the Xilinx hotline. They are willing to
: try fitting close designs.
I'll try that.
Richard.
http://www.rtrussell.co.uk /

Re: Design fits XC9536 but not XC9536XL

If the fitter has not at this stage reported the Prod terms, you
could re-target a 9572XL,(just for the purposes of getting
a complete fitter report!), and then compare with the one below.
It's common for fitter reports to be sparse/terse on failure, so
you are sometimes best to use a 'does fit' pathway
- even if that needs some gyrations ! :)
-jg


Re: Design fits XC9536 but not XC9536XL
: I would expect it to fit. Anything you can do in 2 logic blocks of
: 36V18 can be done in two 54V18.
: I would suggest to place the design into 9536 without XL, save the
: fitter report, run the fitter on 9536XL and compare fitter reports.
The big difference is that the XC9536 report has the 'wire-AND'
option enabled and the XC9536XL has it disabled. My design makes
heavy use of the 'wire-AND' facility, and it has been suggested
that this is not available on the XC9536XL. Is that correct ?
I have raised a Webcase on this issue, but no results so far.
Richard.
http://www.rtrussell.co.uk /

Re: Design fits XC9536 but not XC9536XL
snipped-for-privacy@rtrussell.co.uk wrote in message

XC9500 uses FASTCONNECT switch matrix that is documented to have
wired-AND capability. XC9500XL uses FASTCONNECT II switch matrix that
doesn't have it documented, so I would think it's not there. The only
option is to use pin-compatible XC9572XL part, I guess...

XC9500 uses FASTCONNECT switch matrix that is documented to have
wired-AND capability. XC9500XL uses FASTCONNECT II switch matrix that
doesn't have it documented, so I would think it's not there. The only
option is to use pin-compatible XC9572XL part, I guess...
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