My invention: Coding wave-pipelined circuits with buffering function in HDL

I don't know what to tell you either, do you know what the NASDAQ value represent? Do you think that Lattice only makes FPGA's? Do you think that the stock price for the whole company is good indicator on how many product they sell in a particular group against a survey company that goes out into the industry to find that answer? Do you think eetimes (which has covered electronic news for the past 50 years) is a fake news site with no editorial fact checking?

But lets take your argument and check the stock prices, go to the Nasdaq website and look at the market value of Lattice (LSCC) against MicroSemi (MSCC) and for good measures Xilinx (XLNX), you will be surprised how well Microsemi is doing (even I was). Have a look at the stock prices for the last 5 years, Microsemi is outperforming all of them including Xilinx! Lattice seems to be steady at around 20-40% (well below Microsemi). Lattice has not made any significant changes in the past 5 years. There was a negative dip in 2016 which I assume was caused when Lattice agreeding to be acquired by a Chinese equity firm (subsequently blocked by Trump).

So, making statements like "no one uses Actel/Microsemi FPGAs..." shows you work in an isolated bubble. If you like Lattice FPGA's than fine, no argument from me, but don't use it to justify something you clearly know nothing about.

Back to work.....

Hans

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HT-Lab
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Who said they were using the market cap for the capacity? Companies make reports every quarter. They make very complete reports annually. Lying in these reports is a crime. The information you want is in these reports. The only issue is what exactly is being reported. The Intel info is most likely from then annual report, but there is a lot more to parse and wade through.

You seem to be getting emotional about this. I should believe one set of numbers over another because eetimes is older?

Yes, but next time try not reading what I haven't written.

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Rick C 

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Reply to
rickman

The other way of stating the requirement, using words like those given, is that you need to look at the difference of the minimum delay over PVT of the longest path to the maximum delay over PVT of the shortest path (plus the other factors). The problem of course is that due to the amount of variation in delay over PVT is large enough that you have negative margin, and of course, measuring A unit at A value of PVT, can well give you much better margins than if you need to account for PVT.

One option that might be able to help here is to try and automatically adjust the clock to adjust for changing PVT, at which point you only need to worry about the delta over the part, and the accuracy you could determine the right frequency to run.

Reply to
Richard Damon

Hi,

Actually I don't do anything with Matlab and other advanced tools.

You have to fully understand my scheme: my design has nothing to do with a real wave-pipelined circuit, NEVER!

So there is nothing you have to simulate in Matlab and other advanced tools at all!

In my simulation I even use a direct connection without any logic: C

Reply to
Weng Tianxiang

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