i want to estimate the maximum current that can be consumed of a DDR3L memory bank, consisting of 4 chips with 16 bits data bus width, so in total 64 bit. I need this maximum current for the power supply design (buck converter, 5V -> 1.35V).
I have read through the document TN-41-01: Calculating Memory System Power for DDR3, it shows how to calculate the system power in a very sophisticated manner. But there are a lot of variables i don't know at the moment, like memory access patterns etc.
What about using the highest value of the datasheet, which seems to be often I_DD5B, for example 250mA at a AS4C512M16D3L as the maximum current, so 4 chips consume at max. 1A in total (DRAM Controller of a SoC not included)?
And about the refresh, the datasheets note that a maximum of eight refresh commands can be posted, does this mean, the DRAM executes always only one refresh command at the same time, which refreshes one eight of the DRAM, probably one bank, and the next refresh command refreshes the next part of the dram?
Thanks in advance,