Is there a simple denotation in VHLD of "and" logic between one bit and a vector of bits? The single bit will be extended to the length of the vector first, then a bit-by-bit "and" logic is perform. For example, I have single bit A_OE, B_OE, C_OE and D_OE, and vectors A, B, C, D, I want to do (A_OE and A) or (B_OE and B) or (C_OE and C) or (D_OE and D). Thank you. vax, 9000
Hi vax, 9000,
Can't think of anything built-in or in the standard packages, but assuming A, B, C and D are of equal length, how about
for i in A'LOW to a'HIGH loop result(i)
This is simple to achieve using the for n in m loop type structure.Simply loop along the length of the bit vector performing the #and# at each loop iteration.
and a
example,
and D).
You could try doing
subtype T is STD_LOGIC_VECTOR(A'RANGE);
A and T'(others => A_OE)
It might work,
Or even
A and (A'RANGE => A_OE)
though I think the compiler will then complain that it doesn't know the type of the aggregate,
regards
Alan
-- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
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