Hi Seyior, Are you trolling? ;-) A cursory search back through this newsgroup with Google will show that 'gated clocks' are anathema to everyone here. DON'T DO IT! Cheers, Syms. slices is used (2 slices is unused), the skew of the gated clock in UART is a little large (2-3 ns).…
Read the full replyHi, all:
Implementing a UART(asic core) into XILINX Virtex2 3000-5. Due to 99% slices is used (2 slices is unused), the skew of the gated clock in UART is a little large (2-3 ns).
On debuging, the UART is work well on some boards, however, occur error on other boards. And when I add a skew constraint to limit the skew below 1ns, all boards is ok.
I hope to know, does par tools do setup / hold check with skew analyse. My current mapping tools is ISE5.2.03.
regards, seyior
slices is used (2 slices is unused), the skew of the gated clock in UART is a little large (2-3 ns).
other boards. And when I add a skew constraint to limit the skew below 1ns, all boards is ok.
current mapping tools is ISE5.2.03.
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