Inferring wide adders comprising multiple DSP48s

Is it possible to infer wide adders that require multiple DSP48s? In my experiments with Synplify, I found that it will infer a DSP48-based adder when the inputs are up to 36 bits wide, but when I use 37-bit inputs, the adder is synthesized in fabric. Is there a way to get this to work? XST won't do this either, at least according to the user's guide. -Kevin

Reply to
Kevin Neilson
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From the Synplicity FPGA Synthesis Reference Manual (v8.9)

syn_dspstyle Attribute

In Virtex-4 and Virtex-5 designs, determines if an operator, register, or module/architecture is placed in the DSP48 component.

Reply to
John_H

I don't think any of the synthesis tools do it currently. You can, however write your RTL as a cascade of registered 36 bit adders and as long as the structure matches the DSP48 it should synthesize.

Reply to
Ray Andraka

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