I am developing a partial reconfigurable system and one of the requirements of my system is that one needs to read and update the contents of the BRAM using the ICAP port. My question is that if I configure Xilinx BRAM for a data width greater than 1, say 8 then will all the 8 bits corresponding to the particular byte be in the same BRAM configuration frame? or will they be distributed among multiple frames? If so are there any equations that indicate how the 8 bits within the required byte are distributed in the configuration bit stream.
I read XAPP 151 but that does not give any information in this regard. Though it provides equations for finding the location of a particular bit based on the bit index there is no mention about the bit indices for the 8 bits within the byte.