disadvantages of inferring latches

is generally any circuit or code that retains a signal (or level).

Intended or otherwise.

that would mean a register is a latch. I don't think this is the most common definition (even though it is used sometimes).

Wikipedia quotes the following paragraph

"Sometimes the terms flip-flop and latch are used interchangeably, but there is a distinction. A latch is transparent during a positive clock, whereas a FF is only transparent during a brief interval during the clock transition (edge)."

from

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which is consistent with my understanding (this isn't supposed to prove anything, just my opinion).

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Reply to
mnentwig
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Any time a synthesis tool has ever thrown a warning about "inferred latches", it's talking about transparent latches being accidentally generated inside of combinational code. It doesn't warn me about the thousands and thousands of registers that I've put enables on in the same design, just about

MUX: process(all) begin if sel = "00" then Y

Reply to
Rob Gaddi

laughing out loud... just read this thread backwards. Rabbits... yes.

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Reply to
mnentwig

(snip, smoeone wrote)

The definition changes over time. Some might also use the word "latch" generically, or because it is shorter.

But to be sure, most now say "transparent latch" when they mean that. To be extra sure, "edge triggered" when they don't.

To be more confusing, compare the 7473 and 74LS73.

For the 7473, the setup time is before the rising edge, the hold time after the falling edge. That is, even though it is edge triggered, the data has to be valid and stable long before.

The 74LS73 is more like that you now expect, setup time before the falling edge, and 0ns hold time after the falling edge.

-- glen

Reply to
glen herrmannsfeldt

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