Hi,
I'm looking for a vendor-independent solution to configure RAM contents on an FPGA without rebuilding the RTL. Is there such a thing?
Xilinx has their proprietary data2mem interface that let me replace data in the bitstream file, but it requires a lot of "low-level" work to describe how the RAM is formed from primitives. What I'm looking for is a generic solution, in the same way as putting initial values into inferred RAM, but without having to recompile everything.
I've built my own "homespun" loader using a hardware UART interface, i.e. some FTDI breakout board, and it works well enough within its limitations (extra gates, possibility of bus contention with the design). Now I was wondering, as this seems like such a common problem, is there any known "simple" way for this? JTAG maybe? I did some superficial search here but JTAG seemed to get quite complex, if I stay away from vendor-dependent tools.
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