Is physical synthesis supported for the ACEX 1K devices? I don't know if it will improve the logic synthesis since I have done a lot of hand optimization using specific 4 input equations and "keep" attributes to control the mapping to LUTs. But I find the routing is not very optimal (likely from poor placement) and I expect it could shave some 10% off my worst case paths (~20 nS) if that could be dealt with.
Is physical synthesis available for the 1K50 part and will this help my design?
The next version of the Quartus II Web Edition will support physical synthesis for the Stratix, Cyclone, Stratix II, Cyclone II and Max II families.
Hope this helps.
- Subroto Datta Altera Corp.
etc...
I've never seen a performance difference... but we use synplify. There is a unit size penalty... the hard coded routines have better optimisation. but thats not important... Follow the software rule. Don't use machine code until you have too. theres no point unless your running against the wire or its a specific routine but thats what subroutines are for... even hardware can have a 'hardware' ('vendor') abstraction layer.
Free tools are just a place to start.. if you are considering big volume then you will have simplify, mentor or something similar... in which case it is the same code for both.
I agree. I use mentor leonardo and quartus.
I run a test synthesis on all brand A code with quartus. It works quite well in recent releases. However simplify or mentor tools make it easier to choose devices or verify code as portable.
-- Mike Treseler
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