Is physical synthesis supported for the ACEX 1K devices? I don't know if it will improve the logic synthesis since I have done a lot of hand optimization using specific 4 input equations and "keep" attributes to control the mapping to LUTs. But I find the routing is not very optimal (likely from poor placement) and I expect it could shave some 10% off my worst case paths (~20 nS) if that could be dealt with.
Is physical synthesis available for the 1K50 part and will this help my design?