Hello, This is my first FPGA design and a pretty huge one. Well I believe :=)
First of all, the target is imposed and is an APEX20KE, and I use Quartus.
It is for an XY detectors array 128x128 and thus have 256 head cells, each one with its state machine. Each cell has to work in cooperation with its immediate neighbours in order to resolve some incoming events that can be spread over several consecutive cells. Each cell has a local time counter (100MHz) in order to have the cell's event duration.
Now my problem : Several events may occur at the same time anywhere on the detector, but for simplicity lets consider just one physical event occurence, which translate to a group of several pulses occuring on a set of not disjoint cells (I call this a cluster).
Now each cell compares its local time to a T1 value (fixed delay after the first incoming rising transition) and at the first T1 occurence in the cluster I have to sample all the cluster cells states (input active or not),
**but only for the cells of this cluster** and this have to be done in preferably one, maybe two 100MHz clock cycles (we don't want adjacent clusters to compete for their boundaries).Wouldn't have been the two last conditions that would be almost straightforward, but this makes the exercise difficult.
This almost reduces as : how do I propagate through a group of cells as fast as possible, while controling its propagation. I forgot to mention that the maximum allowed cluster size is 8 cells. Above, all the cluster is rejected and we have time to do this. So we "just" have to be fast on, at worst, 8 cells.
As we don't want "boundary competition" I can't imagine a clocked process for the sampling signal propagation.
I first thought of using the cascade or fast carry chains, but I've had no success.
Another idea was to "ripple sample" the cells, i.e. tie each cell samplingFF clock to the previous cell samplingFF output, and having the D input allowing signal propagation. And after that I have 1 or two resync FFs. Unfortunately I have only 2 clocks available per LAB (10 LE) and this would take too much place.
The best I could come with is (with my FPGA):
- At the first occuring T1, I asynchronously propagate a cell sampling enable signal from one cell to the next, until I encounter a boundary cell. This is hoped to be fast enough to propagate through the max cluster size (8 consecutive cells) within the allowed time (10 or 20 ns).
- then after the sampling period (10 or 20ns) all the allowed cells are sampled, and, hum, et voila.
Unfortunatly, and quite obvioulsy, the fitter complains about a truck load of timing violations, since I have 127 chained LUTs to propagate and control the sampling signal from the first cell to the last one. All I want to do is ensure that the propagation time through a segment (max length = 8) is under control.
How can I do that ?
Any other idea about the design is also welcomed.