Avalon DMA problems


I have a very simple Stratix SOPC system: An Avalon DMA block whose read and write masters both connect to a MegaRAM. The DMA control bus is mastered by Nios.

My DMA blocks registers are set up as:

np_dmareadaddress = 0x10000; // base of MegaRAM np_dmawriteaddress = 0x11000; // 1024 words in np_dmalength = 32; // xfer 32 bytes np_dmacontrol = 0x8C; // do 32-bit xfer, end when length=0 and GO!

I verified the registers by reading them back, and the status reg indicates operation just as I would expect.

When I simulate this system in Active-HDL everything works as expected. On actual hardware, unfortunately, I must always run the DMA operation twice to get the right data into MegaRAM - the first time always writes data to the destination address that is from the PREVIOUS time that I ran the DMA operation. It always write 4 words of old data; after these 4 words, the written data is current and correct.

The only way I can rationalize this is that the FIFO inside the DMA block is writing data to the destination before the source data has been read into it.

My questions are:

- Can I use the Avalon DMA block to DMA to/from MegaRAMs? Or do the source and/or destination resources have to be streaming slaves? (ie. can a streaming master such as DMA work with non-streaming slaves such as MegaRAMs?

- Why does simulation give me the correct results? Does it have to do with me running on Stratix, whereas Active-HDL may assume I'm running on Apex, etc?

- Is there a bug with the DMA block, or am I doing something stupid?

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The Altera DMA block has bugs if "Use ESB/EABs" is selected in its GUI on Stratix. I don't know about other architectures. The default option works properly in this scenario. I'm guessing ESBs have different timing than TriMatrix and therefore FIFO draining does not work properly.

-- Pete

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Peter Sommerfeld

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