Article about using Non-Project Mode

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Thanks. I'm in the sim phase on my project right now but when I get back into PAR I'm going to check this out.

I have closed access to the draft of the article because I shared it for some time just to get some reviews and suggestions.

I'll publish the article as soon as it is reviewed by my employer.

Kevin, if you have an Google account you can request access to the draft and I'll grant it to you.

It looked fine to me. It did suffer slightly from falling into the strangely common trap of assuming FPGA=Xilinx, so maybe that should be signposted up front a bit more.

(It's possible to do similar things with Altera but I think the article would need too much restructuring to account for different ways of doing things. I'm not familiar enough with Lattice or Microsemi to comment on those toolchains)

Theo

Thank you for your response.

On one hand, I tried not to make the article too Xilinx-specific because I believe that other tool chains have the same problems and that they likely to have similar modes of operation. On the other hand, I do not have non-Xi linx experience to make any specific advice for other toolchains. I see tha t I need to rework the beginning of the paper to make it clear.

I'd avoid trying to be too generic. I've set up Makefile based flows under both Xilinx (ISE) and Altera Quartus and they have nothing to do with one another. Totally different paradigms, problems, syntaxes, etc.

As near as I was able to tell while you had that document publicly available, you're trying to describe how to a non-project flow under Vivado at this current point in time. That's valuable and helpful. If you haven't made it public again about a month from how I'll probably start harassing you for a copy by email. Better to do that well than to half-ass a generic document that almost by definition can't be right.

I need to accomplish several formal steps before publishing it. It uses some code I've written on my workplace and, therefore, I must obey corporate rules of publishing articles. As soon as I get the article reviewed by my boss and colleagues, I'll try to publish it on fpgarelated.com and may be somewhere else.

and I'll grant it to you.

Ilya, Thanks for the document. You inspired me to use non-project mode and now t hat I have a script for one of my projects I can just keep reusing it. The only thing I'd say about your document is that I think it had some Windows

-specific stuff which wasn't obvious to me at first.

There is also a brief intro to non-project mode in the Vivado Quick Referen ce:

t and I'll grant it to you.

that I have a script for one of my projects I can just keep reusing it. T he only thing I'd say about your document is that I think it had some Windo ws-specific stuff which wasn't obvious to me at first.

ence:

It's finally published on edn.com !

Kevin, I'm so glad that I inspired you! In fact, it was a goal of the article to encourage more people to use this mode, so that IDE developers pay more attention to this way of managing pro jects.

I hope that some inconvenience of using IPs in this mode will not discourag e you. :) I am planning to write another article devoted to this problem. I hope I wi ll find time for doing some research on this matter and for writing article .

Nice :)

I should probably have a play some time and try and do similar for Altera tools. It's fairly simple - the project settings output by Quartus are 'just tcl', so in theory it should be drivable from a tcl script. At the moment we build from a Makefile but we still have a nominal project with the tcl settings.

I was pleasantly surprised to discover that there's a variety of recipes for putting Quartus inside Docker images, so it looks like there's quite a bit of interest in scripted builds.

(My interest here is running the Altera JTAG stack inside Docker, so it's easier to plug [lots of] FPGAs into the test environment without them conflicting. We already do this, but Docker will help cleaning up better)

Theo

Don't forget to mention my article in yours one :)