What is TI PRU-ICSS processor core?

They are in the Beaglebone SOC among other places. The instruction set presumably originated in some weird legacy part. It is ... idiosyncratic. But there are C and C++ compilers for it now.

Web search on "beaglebone pru" finds good info. Maybe start here:

By "legacy" part you mean the first TI ARM that used it? Or did it come from an unrelated design?

I don't know its origins but just looking at its instruction set, it seems to come from an earlier era of cpu design than what we usually deal with today. Its heritage may have been in industrial automation rather than computing. It's not my area but I think PLC's originally didn't have the features of normal microprocessors, but gradually acquired them, and now they have normal microprocessors inside.

Maybe the instruction set is optimized for it's application and construction. I haven't looked at it in detail, but I've been told it isn't intended to be general purpose.

I'm pretty sure they aren't from PLCs.

I've only had a very quick look at the PRU information on the web, but it doesn't look like a PLC-optimised cpu to me. For PLC work, you expect lots of bit handling instructions to suit the chains of and/or "relays" in typical PLC programming. A targeted cpu is also likely to support things like timers in the instruction set. You'd see BCD as a strong alternative to binary (not just BCD arithmetic instructions, but things like indexed addressing using BCD offsets), and you'd expect a heavy bias towards 16-bit and bit types.

Thanks Paul, interesting stuff.