A decade after my last 80186-based product, I need a uP that can DMA from RAM (internal or external) to a parallel bus peripheral (GPIB - yeah, I know: who uses GPIB anymore?) but I don't see modern chips with this capability. What I'm talking about is a DMA controller that can be configured to do the following:
0) external device signals DREQ 1) uP finishes whatever instruction it's in the middle of 2) uP releases the bus to the DMAC 3) DMAC reads from source (RAM, or another peripheral) 4) DMAC writes to the destination address (peripheral de-asserts DREQ) 5) DMAC releases the bus 6) uP goes about its business until the next DREQ assertIt's a very low-overhead method to dump huge data to/from a peripheral that may be constrained by the outside world to take/give data at arbitrary times. So far, I've looked at Blackfin and Coldfire. Maybe they can do it, but I haven't seen it in the data sheets. Their DMA engines look fine at shoveling data internally, but where's DREQ? What am I missing?
TIA, Bob