The _simplest_ solution is to pulse _SS at the end of each byte (or packet). The receiving end should be implemented to reset its rx state machine when _SS goes high.
If you don't implement the _SS line, and you are using a hardware SPI peripheral, it can be tricky; if you need to sync in to an arbitrary bitstream you'll have to implement shifting in your software since the SPI peripheral won't necessarily be lined up with the byte boundaries of the bitstream. This is made vastly more complex if you have a multimaster system. _SS is the best way to go IMHO - once the line goes high, EVERYONE on the bus knows that it's time to reset.
Larwe's solution is quite pratical but say you don't want to do that because of some undefined reasons then adding some kind of sync data with in the data stream might work;-) For example, adding checksum of every 5 bytes in the data stream. But ofcourse it will cost you over head but an easy software solution for hardware SPIs.
IMO, consider the device as arbitrary (byte-)length of shift registers. With the CS signal common to all latch inputs, the content ist latched into the internals.
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