I am working with ST micom and have some questions on SPI. I have asked on ST forum that I can see SCLK when micom is master and sending data, but I can't when micom is master and receiving data. Then someone answered that I should send null data to active SCLK even when I want to receive data. Is this right method? And another question. When master micom is sending out clock, how micom can know if signal on MISO is valid data or not? I have tried above method but SPI interrupt does not occur when I have set receive buffer not empty interrupt. though data in MISO is data not valid. Please answer these questions. Thanks.
SPI questions.
Nov 07, 2007
1 Replies
Yes.
How could it possibly know? The bit is either high or low on each clock, and the microcontroller can't tell when it's in between. It's the responsibility of the hardware and software to make _sure_ that the data on MISO is valid when it's being clocked.
If you're the master, then you should probably interrupt on the transmit buffer empty.
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com
Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
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