Simple gate array to replace 4 ls ttl + eprom

Chris Quayle schrieb:

depends on the definition of 'low power' and 'low cost'

choice 1: Lattice XP3, small flash PFGA with block rams inside (6KByte), cost 8USD? (depends on qty)

if the power consumption is too much some quicklogic OTP fpgas could be candidates.

in both cases the NRE costs are virtually 0 as you can use free software tools and low cost eval boards. in case of quicklogic they provide free 'webasic' samples I think, but you better get the design work first time:)

Antti

Depends on the microprocessor. A Texas Instruments F2812 will do about

50Mips when running from flash, much more when time critical sections run from RAM. That's between 125000 to 300000 instructions per each 400 Hz cycle. Still, a small CPLD will probably be cheaper.

Thanks for the replies - I spent a couple of hours on google before posting, but there seems to be a very wide variety of devices available, most of which also seem to have dozens of pins, when the design needs only ~ 2 inputs and 6 outputs. The present hardware uses one 8 bit and one divide by 12 ripple counter, a 4 bit comparator and an 8 bit addressable latch + the eprom.

It might just be that one or more pal type devices would be more appropriate, but have no feel for what programmable logic complexity would be required to synthesise the above collection of devices, without under or overspecifying. Too many years software design = out of date on the hardware side...

Regards,

Chris

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Greenfield Designs Ltd
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That Logic will easily fit into a 32 Macrocell CPLD.

Can you post the EPROM data ? - if it is a couple of dozen bytes (nibbles?), that will likely also fit into a slightly larger CPLD, so you can drop the whole design into one package. ROM tables do compress when you do a table -> product term compile.

For larger sine tables, it is practical to use a small SO8 SPI FLASH device, as the storage element; they are very cheap/small.

For 5V, look at Atmel ATF1502ASL, or ATF1504ASL : PLCC44 to TQFP44 JTAG In system programmable, low power.

For 3V/1.8V core, look at ATF1502BE / ATF1504BE(soon)

You can also add fast-protection, in the CPLD if you want, or get more precision.

-jg

Or a SPI EEPROM..

Well, 400 Hz, 6 steps per quadrant, 4 quadrants... thats 9600 pulses per second per output. If you want 8 bit thats 2.4576 MHz if you were updating on every tick. Seems like a little FPGA or even a CPLD is up for that.

However I can't see what a simple micro can't do it either. Elsewhere in this ng there is discussion of the MC9S12GC, which has six pwm outputs. Even without PWM support it looks quite doable to me. Whats wrong with

write to port nop nop nop... write to port nop...

the pattern is currently in a EPROM so it clearly doesn't change dynamically. The issue is only the shortest time between pin pattern changes.

On a related issue, do you use a fixed repetition rate for the pwm pulses or do they change - you should be able to reduce the harmonic content by moving the pulses about i.e. think of it as 6 pulse every quadrant that can be anywhere and any length that fit.

Peter

Have a look at the Hitachi 30f48 micro. I did this same job on it

10+years ago and it certainly is fast enough, unless there is something else you haven't mentioned.

Started off by looking at micros. Seemed like the most flexible solution and could use an a-d for control, voltage regulation, current limiting etc. Software timing loops of any kind are too critical and flaky to consider though. Looked at 8051, msp430 series and others for 3 x 8 bit timers directly usable (ie:= direct hardware outputs) for pwm. Micros that do have > 2 timers also seem to come with loads of baggage like can bus interfaces etc, which only adds tothe cost. What's needed is a readily available bare bones fast cpu with say, 1k flash, 1k ram, 3 or more 8 bit pwm hardware outputs and perhaps a comparator or 8 bit a-d. Not bga or some other unfeasably small package either, though many are not available in pdip or even soic. Manufacturers spin can make it difficult to find a suitable device as well. For example, go to the Philips web site and look at 8051 series and most of the devices that say 4 timers actually have two real timers + rtc + watchdog, but you have to waste time going to each data sheet to find this out.

Interesting - hadn't even thought about that. Do you mean jitter each pulse width and position about a centre line - how would this reduce harmonic content ?...

Chris

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Jim Granville wrote:

Thanks for the pointers. The eprom data is 6 x 16 steps of 4 bits, with a fifth data bit used in the logic. Other 3 bits are unused.

Spent this afternoon with Atmel - downloaded the WinCupl package first and had a look, but it looks a bit palasm / microcode level. Then had a look at Prochip Designer, which you get a 30 day license for. The schematic entry looks good, but the lowest cost programming lead costs $150 (can't find a schematic on site) and the post 30 day license fees are high. It looks like they have pulled together applications from various vendors, but this may be just a stopgap measure while they get their own integrated package together. One would think that the vendors would have tightly integrated free tools without restriction for their devices by now, but application complexity and licensing issues may preclude this. In summary: The initial investment in infrastructure, time and cost for even a trivial design is still quite high and changing vendor probably means starting again. What is lacking afaics, is a zero or very low cost / risk way to *evaluate* programmable logic devices, to include enough info to build evaluation boards rather than buy. Also had a look at opencores.org, which has links to VHDL tutorials as well as interesting and obscure stuff like a cordic processor design. Maybe the open source route will be the way to go long term. The common thread so far looks like VHDL, which is almost understandable with no prior knowledge, so that may be the investment in time that I need to make. Much of the open source projects talk VHDL as well, so far as I can see.

Will have a look at the other vendors this week, but it's starting to look like a micro + a little ttl for the high speed stuff would be a better choice, both in terms of cost and flexibility. Chris

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Greenfield Designs Ltd
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Embedded Systems & Electronics: Research Design Development
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A little wink-wink, nudge-nudge to your distributer will often get you a free license.

The Atmel AT89LP21x, and AT89LP2052 get close - (1K ram is never going to make sense in a 1K Flah device)

If you want dedicated PWM HW, with a fast core, then look at : Infineon XC88x family SiLabs family - F330 comes in DIP20, or their newer C8051F41x series Ramtron VRS51L3074 - claims 8 channels of PWM

Or, you can swallow it into a CPLD, and avoid any 'new' software...

'best'? choice depends on your present host controller.

-jg

So the 6 is the phases ? - The PLD can handle the Phase indexing into a single table.

We use a triangle (up/dn) counter which folds the table, so this looks like it would reduce to 16x4 ROM, which will fit into a 32 MC device. [In a cpld you want to reduce the ROM by design, as much as possible, as ROM via product terms is doable, but not efficent]

eg 7 Segment display ROMS map quite well into CPLDs

For this level of problem, that's fine! :)

WinCUPL is stable, compiles in < 1 second, and gives a degree of HW control that VHDL lacks. It is also easy to learn. WinCUPL _can_ create JEDEC test vectors.

WinCUPL does not have timing simulation, or high levels of abstraction, but for CPLDs that's OK. You can get VHDL/Verilog reports from the system, if you really want timing simulations.

We use their new ATF15XX-DK3, ~$100, includes an AS/BE JTAG cable, and VregADJ/Zif44/LEDS/Buttons for PLD design evaluation.

The Atmel ISP Sw also supports 3 types of Byteblaster cable, if you happen to have those (or a circuit of one....)

VHDL is good for larger design projects ( eg FPGAs ), but it makes little sense to me, to use 600Mbytes of tool chain, to compile some few dozen lines of source code, to 50-100 product terms in a CPLD :)

We often use uC+CPLD, where you can use each to their strengths.

-jg

You might also want to have a look at the CPLD development board from Software Crew. This allows you to test the logic function of a CPLD. There is an AVR which can feed the CPLD with stimuli, and a memory which allows storage of the resulting outputs. The data can be read back and stored as a vcd file so you can open it in any decent verilog simulator to check what really happened.

There is also a prototyping area where you can put different kind of logic/MCUs (in PDIP packages)

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Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may not be shared by my employer Atmel Nordic AB

Hi Ulf,

No Price ?

No details of actual vector tests supported ?

Interesting approach: this is a very large PCB, and it is a "PC-less" system, with a local 8 button keypad and large LCD readout.

No support for the new ATF1502BE ?

I prefer a PC_TEXT-centric design environment, where the main tool is a Programmer's Text Editor, set up for a single-key CUPL Build/FIT.

-jg

[snip]

Here are some interesting ideas about "magic sinewaves" for reducing harmonic content

Peter

Have decided a micro solution is the best bet because of the flexibility and built in a-d converter etc. Have looked at several vendors and Silabs looks like amazing value with a complete out of box working kit for under $70. It's particularly attactive because we already have Keil C here and it would probably only mean moving the device header files over to have a complete dev kit for any rom size at very little cost. There is a pdip version for one of the devices, but, predictably, isn't the device I would choose. The 3mm square packages will be fun and games in production, but will probably build a small dil daughter board to make it more easily adapted to a variety of projects. There are even examples with dual channel 24 bit a-d, which would be usefull for other projects.

The key thing on all these micros seems to be the PCA or count compare subsystems, which means you can have (say) 3 pca channels to provide 3 independant pwm outputs from a single timer. It's not something that's immediately obvious from the top level spec if you are doing a quick web survey, but is in the data sheet if you dig (who has time to look at data sheets for dozens of devices ?). Even the MSP430, which I bought a kit for at vast expense back in 1997 and never found a project for, looks like it (some variants) could be coerced into providing 3 pwm channels from one timer. The development support for msp doesn't include an out of the box kit, just a list of vendors to get a collection of bits from, but could forgive that - it's such a clean architecture.

As for programmable logic, it's just too much hassle. Don't have the time to learn / program microcode. If you install all the "free" limited license vendor tools, you end up with all kinds of license stuff all over the machine and registry and who knows what else, half of which probably doesn't go away when you uninstall the package. The situation seems more or less as per 5 years ago: Chip vendors trying very hard to provide eval kits at reasonable cost, but the market still very much locked down by the big eda software vendors. Some of the full license prices are outrageous and the market seems to be at the same stage as pre Gnu compiler days, when major vendors were charging thousands or more pounds for a C cross compiler. I think we paid 6K pounds per seat for Microtek Masterworks at one site I worked at in 1995. Thankfully there are now alternatives. I think open source is the only way to crack the nut long term...

Chris

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Greenfield Designs Ltd
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Embedded Systems & Electronics: Research Design Development
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Hi Peter,

Thanks for that, though not sure how usefull it would be in practice. Assuming you have a good sine wave model and low pass filtering on the output, the higher order harmonics should be fairly insignificant anyway...

Chris

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Greenfield Designs Ltd
-----------------------------------------------------------
Embedded Systems & Electronics: Research Design Development
Oxford. England. (44) 1865 750 681

SiLabs newer devices ( as expected ) give more functions for the dollar, and their device I like for new designs would be the F41x : this has 5V operation, so can drive MOSFETS properly, plus 12bit ADC/DAC. These devices also have 24Mhz CAL_OSCs inbuilt.

You are probably right to choose a uC, in your app, as CPLDs make most sense when the uC peripherals don't quite make the grade....

However, your tools summary is not fully correct for CPLDs: We use Atmel's WinCUPL here ( free, no timed licenses ), and a Text editor (also free).

The latest changes to Notepad++ (Sourceforge v3.7) make this work nicely with WinCUPL, in command line mode.

That gives appx an ~10MB tool-chain system, which is much easier to learn, and manage, than a ~600MB+ FPGA toolchain, and matches the 'smallish resource' that CPLDs have, quite well.

-jg