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Re: Cygnal/Silabs F12x MAC0, does it work?

Hi Gary,

If you've tried several different chips, then maybe > it's the IDE that is the problem.

I supposed that the IDE might have a problem reading out the MAC0 registers. That's why I did move the result from the MAC0ACCx registers to variables in the DATA space, and watch these variables. But these variables are always zero too :-(

You might want to contact the IDE maker and > see if they have a problem.

It's the original IDE from Silicon Labs, latest version 1.9 downloaded from their website.

Of course I asked them before I posted the problem here. No answer from them since 3 days :-(

Michael

Reply to
Michael Koch
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Hi,

yes, SFRPAGE = 3

have you already tested the MAC0?

Michael

Reply to
Michael Koch

Hi Gary,

that's correct.

No, there is no simulator mode.

seems to be coming through just fine.

agreed. Everything else is working fine in these chips. There have never been any problems with the JTAG interface. Michael

Reply to
Michael Koch

have you set SFRPAGE register? "Michael Koch" ???? news: snipped-for-privacy@gmx.net...

Reply to
enst

MAC0ACC3 should be 0 and MAC0ACC2 should be 03 with the values you are using.

Sometimes there can be bad chip batches, but you tried a 122 and a 123 and the odds that those two would exhibit the same problem would be small, as far as I know. Of course, for all I know the 123 is just a 122 in a different package and they might be from the same batch.

It's probably not something to do with external hardware as the multiplier is completely internal.

It's not an SFR watch window problem since you're reading them into low RAM as well and they confirm that it's 0. The MAC status seems to read fine and it also says it's 0.

Does the IDE have a simulator mode? If so, does that work?

I wouldn't think it has anything to do with any JTAG weirdness as other stuff seems to be coming through just fine.

I'm stumped. Hopefully Silicon Labs will be able to shine some light on what is going on.

Reply to
Gary Kato

Hi Gary,

I have already tested at the default clock and at 99MHz. Same negative results.

Michael

Reply to
Michael Koch

About the only other thing I can think of to try is to use a faster clock. On reset, the internal 24MHz oscillator is used and that is divided by 8 to generate the SYSCLK. You might try changing it to divide by 1. People tend to operate at faster speeds so maybe the MAC wasn't tested at the default 3MHz SYSCLK.

Reply to
Gary Kato

I have tested it on Keil's uV2 with C8051F120 and everyting works as supposed...

regards

Dejan

Reply to
Deni

Hi Dejan,

it's good to hear that it works. Seems that I got some early prototypes with a bug in the silicon. Hopefully SiLabs will shine some light on this problem soon...

Thanks, Michael

Reply to
Michael Koch

Hi all,

the problem is solved. Silicon Labs answered that it's a bug in the silicon in F122/F123 controllers that were shipped before October 31, 2003.

Thanks, Michael

Reply to
Michael Koch

So much for their quality control.

Reply to
Gary Kato

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