Re: Are 4000 interrupts per second a problem for AVR?

why not just modify your board with a cut and a piece of wire - much easier all round!

-- Sell your surplus electronic components at

small

'manually.'

task.

This should not be a problem. I am running an ISR at 19200Hz which reads 4 input lines and runs 4 software uarts. No sweat.

Meindert

On 14/03/2006 the venerable George Orwell etched in runes:

Actually to produce a 4kHz signal you're looking at an 8kHz ISR rate. One ISR for each transition. With an 8MHz crystal that's 1000 clock cycles per ISR.

If you can't change the pin then you might be able to change the buzzer to a self-oscillating one that only needs to be switched on and off. Seems like a better solution to me.

I've also had 10 kHz interrupt routines on an AVR, running at 8 MHz. But I think the tightest challenge was running a 38.4 kbaud software UART with 4 times sampling (153.6 kHz interrupts) on a 7.37 MHz AVR, giving precisely 48 clock ticks between each interrupt.

So 4000 Hz is no problem. If you want to minimise the overhead, write the ISR in assembly. Figure out how many (if any) registers you need, and reserve them from use by your compiler. That way you don't need any context saving or restoring, except perhaps for the status register, and all your ISR-critical data is in registers when the code starts.

I've done a 2kHz piezo using a 4MHz '05 (1MHz bus rate) (interrupt every 250usec), with enough time left over to do 32-bit PID control,

Best regards, Spehro Pefhany

My record for real time response is 250,000 context switches per seconds on an HPC16083

Not too bad for a CPU with just a few MIPS. When there is a will, there is a way.

To produce 4000hz you would actually need 8000 interrupts a second if you intend to make a square wave.

Whether you can do this depends on your other timing requirements. If you can afford to only do only the buzzer, no problem.

The HPC has more than just a few MIPs - can't they run at up to 40 MHz? (Our HPC apps never used more than 10 MHz.) About 15 years ago, they were one of the fastest microcontrollers available. Still, at 250,000 context switches a second, there can't have been much left cpu time left after the context switch overhead?

Only the HPC46100, the others were limited to 16-20 Mhz, and it was an accumulator based architecture with a few address register.

Nope, the memory to memory address mode helped a lot.